Packet data transfer scheme is introduced for intrachip data transfer to solve an interconnection problem. Double transmission lines are provided as a platform of the micronetwork. A protocol suitable for intra-chip data transfer is proposed to make a router as simple as possible. An application to a parallel VLSI processor is also discussed. In comparison with a multi-bus architecture the parallelism can be greatly increased under the same chip size because of the compactness of the micronetwork.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 2005 Dec 1|
|Event||IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan|
Duration: 2005 May 23 → 2005 May 26
ASJC Scopus subject areas
- Electrical and Electronic Engineering