VLSI architecture based on packet data transfer scheme and its application

Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi

Research output: Contribution to journalConference article

7 Citations (Scopus)

Abstract

Packet data transfer scheme is introduced for intrachip data transfer to solve an interconnection problem. Double transmission lines are provided as a platform of the micronetwork. A protocol suitable for intra-chip data transfer is proposed to make a router as simple as possible. An application to a parallel VLSI processor is also discussed. In comparison with a multi-bus architecture the parallelism can be greatly increased under the same chip size because of the compactness of the micronetwork.

Original languageEnglish
Article number1464955
Pages (from-to)1786-1789
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
Publication statusPublished - 2005 Dec 1
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: 2005 May 232005 May 26

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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