Visualization of Gate-Bias-Induced Carrier Redistribution in SiC Power DIMOSFET Using Scanning Nonlinear Dielectric Microscopy

Norimichi Chinone, Yasuo Cho

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

Carrier profiling in the cross section of a gate-biased silicon carbide power double-implanted MOSFET is demonstrated with a newly developed measurement system that utilizes super-higher-order scanning nonlinear dielectric microscopy. Two techniques that have features that complement each other were proposed and demonstrated. In all measurements, the tip-sample voltage difference was cancelled during gate-source voltage (VGS) application. Variation in the VGS-dependent carrier distribution was reasonably determined using both of the proposed techniques.

Original languageEnglish
Article number7486071
Pages (from-to)3165-3170
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume63
Issue number8
DOIs
Publication statusPublished - 2016

Keywords

  • Carrier profiling
  • scanning nonlinear dielectric microscopy (SNDM)
  • semiconductor device measurements
  • silicon carbide (SiC) devices
  • super-higher-order (SHO) SNDM

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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