Visualization of Gate-Bias-Induced Carrier Redistribution in SiC Power DIMOSFET Using Scanning Nonlinear Dielectric Microscopy

Norimichi Chinone; Yasuo Cho

doi:10.1109/TED.2016.2571780

Visualization of Gate-Bias-Induced Carrier Redistribution in SiC Power DIMOSFET Using Scanning Nonlinear Dielectric Microscopy

Norimichi Chinone, Yasuo Cho

Information Devices Division

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

Carrier profiling in the cross section of a gate-biased silicon carbide power double-implanted MOSFET is demonstrated with a newly developed measurement system that utilizes super-higher-order scanning nonlinear dielectric microscopy. Two techniques that have features that complement each other were proposed and demonstrated. In all measurements, the tip-sample voltage difference was cancelled during gate-source voltage (V_GS) application. Variation in the V_GS-dependent carrier distribution was reasonably determined using both of the proposed techniques.

Original language	English
Article number	7486071
Pages (from-to)	3165-3170
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	63
Issue number	8
DOIs	https://doi.org/10.1109/TED.2016.2571780
Publication status	Published - 2016

Keywords

Carrier profiling
scanning nonlinear dielectric microscopy (SNDM)
semiconductor device measurements
silicon carbide (SiC) devices
super-higher-order (SHO) SNDM

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/TED.2016.2571780

Cite this

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title = "Visualization of Gate-Bias-Induced Carrier Redistribution in SiC Power DIMOSFET Using Scanning Nonlinear Dielectric Microscopy",

abstract = "Carrier profiling in the cross section of a gate-biased silicon carbide power double-implanted MOSFET is demonstrated with a newly developed measurement system that utilizes super-higher-order scanning nonlinear dielectric microscopy. Two techniques that have features that complement each other were proposed and demonstrated. In all measurements, the tip-sample voltage difference was cancelled during gate-source voltage (VGS) application. Variation in the VGS-dependent carrier distribution was reasonably determined using both of the proposed techniques.",

keywords = "Carrier profiling, scanning nonlinear dielectric microscopy (SNDM), semiconductor device measurements, silicon carbide (SiC) devices, super-higher-order (SHO) SNDM",

author = "Norimichi Chinone and Yasuo Cho",

note = "Funding Information: This work was supported in part by the Japan Society for the Promotion of Science (JSPS) through the Grant-in-Aid for Scientific Research S under Grant 23226008, in part by the JSPS through the Grant-in-Aid for Scientific Research A under Grant H1602330, and in part by JSPS for Young Scientists under Grant 268084. Publisher Copyright: {\textcopyright} 1963-2012 IEEE.",

year = "2016",

doi = "10.1109/TED.2016.2571780",

language = "English",

volume = "63",

pages = "3165--3170",

journal = "IEEE Transactions on Electron Devices",

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AU - Chinone, Norimichi

AU - Cho, Yasuo

N1 - Funding Information: This work was supported in part by the Japan Society for the Promotion of Science (JSPS) through the Grant-in-Aid for Scientific Research S under Grant 23226008, in part by the JSPS through the Grant-in-Aid for Scientific Research A under Grant H1602330, and in part by JSPS for Young Scientists under Grant 268084. Publisher Copyright: © 1963-2012 IEEE.

PY - 2016

Y1 - 2016

N2 - Carrier profiling in the cross section of a gate-biased silicon carbide power double-implanted MOSFET is demonstrated with a newly developed measurement system that utilizes super-higher-order scanning nonlinear dielectric microscopy. Two techniques that have features that complement each other were proposed and demonstrated. In all measurements, the tip-sample voltage difference was cancelled during gate-source voltage (VGS) application. Variation in the VGS-dependent carrier distribution was reasonably determined using both of the proposed techniques.

AB - Carrier profiling in the cross section of a gate-biased silicon carbide power double-implanted MOSFET is demonstrated with a newly developed measurement system that utilizes super-higher-order scanning nonlinear dielectric microscopy. Two techniques that have features that complement each other were proposed and demonstrated. In all measurements, the tip-sample voltage difference was cancelled during gate-source voltage (VGS) application. Variation in the VGS-dependent carrier distribution was reasonably determined using both of the proposed techniques.

KW - Carrier profiling

KW - scanning nonlinear dielectric microscopy (SNDM)

KW - semiconductor device measurements

KW - silicon carbide (SiC) devices

KW - super-higher-order (SHO) SNDM

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Visualization of Gate-Bias-Induced Carrier Redistribution in SiC Power DIMOSFET Using Scanning Nonlinear Dielectric Microscopy

Abstract

Keywords

ASJC Scopus subject areas

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