Visualization of gate-bias dependent carrier distribution in SiC power-MOSFET using super-higher-order scanning nonlinear dielectric microscopy

Norimichi Chinone, Yasuo Cho

Research output: Contribution to journalArticlepeer-review

Abstract

Carrier distributions in cross-section of operated SiC power MOSFET were measured using super-higher-order scanning nonlinear dielectric microscopy. Two measurements were carried out; depletion layer distribution analysis for "on"/"off" state and detailed analysis of gate-source voltage (V GS) dependent carrier distribution. In all measurements, tip-sample voltage difference was kept canceled during V GS application in order to avoid unexpected carrier redistribution due to the tip-sample voltage difference. As a result of the former experiment, difference of depletion layer distribution between "off" and "on" state was visualized. An electron channel formation at "on" state was also visualized. Moreover, in the latter experiment, detailed carrier re-distribution depending on the V GS was clearly visualized.

Original languageEnglish
JournalMicroelectronics Reliability
DOIs
Publication statusAccepted/In press - 2015 May 24

Keywords

  • Carrier profiling
  • Scanning nonlinear dielectric microscopy
  • Scanning probe microscopy
  • SiC power device

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Surfaces, Coatings and Films
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Safety, Risk, Reliability and Quality

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