Via Reveal and Backside Processing

The wafer or chip stacking using the TSV and the microbump is the key for fabricating 3-D LSIs. A wafer or chip has to be thinned from the backside before 3D stacking. Therefore, the backside processing is very important for fabricating reliable 3-D LSIs. So far various kinds of 3-D integration technologies have been proposed. However, two kinds of technologies, namely the via-middle (via-first) process and the back-via process, are considered to be promising as a 3-D technology for mass-production. In this session, the backside processing for the via-middle technology and the back-via technology is discussed. Microbump and RDL formation is also included in the backside processing. In the via-middle technology, the base of Cu-TSV has to be exposed after the Si thinning from the backside and hence the backside surface of thinned Si substrate might be contaminated by Cu impurities during via-reveal processing. Therefore it is important that the Si substrate thinning by mechanical grinding and CMP is stopped just before exposing the base of TSV to avoid the Cu contamination on the thinned Si surface. The back-via technology has an advantage of low cost. However all process steps for TSV formation have to be performed from the backside at the processing temperature below 300°C. Therefore, it is not easy to fabricate TSVs with a small diameter and high aspect ratio. The Cu contamination is still serious issues even in the back-via process technology. Therefore it is very important to form the Cu gettering layer at the backside Si surface and the Cu diffusion barrier such as silicon nitride film on the backside in both the via-middle technology and the back-via technology.