Very low power consumption Viterbi decoder LSIC employing the SST (scarce state transition) scheme for multimedia mobile communications

K. Seki; S. Kubota; M. Mizoguchi; S. Kato

doi:10.1049/el:19940460

Very low power consumption Viterbi decoder LSIC employing the SST (scarce state transition) scheme for multimedia mobile communications

K. Seki, S. Kubota, M. Mizoguchi, S. Kato

Research output: Contribution to journal › Article › peer-review

15 Citations (Scopus)

Abstract

A very low power consumption Viterbi decoder LSIC has been developed by using a low supply voltage 0.8μm CMOS master slice process technology. By employing the scarce state transition (SST) scheme, this LSIC achieves a drastic reduction in power consumption below 600μW at a supply voltage of IV when the data rate is 1152kbit/s and the bit error rate is less than 10^-3. This excellent performance has paved the way to employing the strong forward error correction and low power consumption portable terminals for personal communications, mobile multimedia communications, and digital and audio broadcasting.

Original language	English
Pages (from-to)	637-639
Number of pages	3
Journal	Electronics Letters
Volume	30
Issue number	8
DOIs	https://doi.org/10.1049/el:19940460
Publication status	Published - 1994 Jan 1

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el:19940460

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abstract = "A very low power consumption Viterbi decoder LSIC has been developed by using a low supply voltage 0.8μm CMOS master slice process technology. By employing the scarce state transition (SST) scheme, this LSIC achieves a drastic reduction in power consumption below 600μW at a supply voltage of IV when the data rate is 1152kbit/s and the bit error rate is less than 10-3. This excellent performance has paved the way to employing the strong forward error correction and low power consumption portable terminals for personal communications, mobile multimedia communications, and digital and audio broadcasting.",

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AB - A very low power consumption Viterbi decoder LSIC has been developed by using a low supply voltage 0.8μm CMOS master slice process technology. By employing the scarce state transition (SST) scheme, this LSIC achieves a drastic reduction in power consumption below 600μW at a supply voltage of IV when the data rate is 1152kbit/s and the bit error rate is less than 10-3. This excellent performance has paved the way to employing the strong forward error correction and low power consumption portable terminals for personal communications, mobile multimedia communications, and digital and audio broadcasting.

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Very low power consumption Viterbi decoder LSIC employing the SST (scarce state transition) scheme for multimedia mobile communications

Abstract

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