Vertically integrated processor and memory module design for vector supercomputers

Ryusuke Egawa, Masayuki Sato, Jubee Tada, Hiroaki Kobayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

To overcome the memory and power wall problems on a high performance microprocessor for supercomputer systems, the reduction in memory access latencies and its power consumptions is urgently required. Recently, a 2.5D integration technology, which can integrate multiple chips on a silicon die by using vertical interconnects, are expected as key technologies to overcome these problems. Under this situation, this paper explores the design space of a processor and memory module for vector supercomputers using a vertical integration technology. In this study, both a processor and a memory of vector supercomputers are integrated in one silicon die as a single module, and its performance and power are evaluated by leading scientific applications. The evaluation results demonstrated that the 2.5D integration reduces the energy consumption by 83% compared to the conventional PCB implementation.

Original languageEnglish
Title of host publication2013 IEEE International 3D Systems Integration Conference, 3DIC 2013
DOIs
Publication statusPublished - 2013 Dec 1
Event2013 IEEE International 3D Systems Integration Conference, 3DIC 2013 - San Francisco, CA, United States
Duration: 2013 Oct 22013 Oct 4

Publication series

Name2013 IEEE International 3D Systems Integration Conference, 3DIC 2013

Other

Other2013 IEEE International 3D Systems Integration Conference, 3DIC 2013
CountryUnited States
CitySan Francisco, CA
Period13/10/213/10/4

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Computer Science Applications

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