VERTICAL ISOLATION IN SHALLOW n-WELL CMOS CIRCUITS.

Alan G. Lewis, Russel A. Martin, John Y. Chen, Tiao Yuan Huang, Mitsumasa Koyanagi

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

Vertical punchthrough in a shallow conventional n-well suitable for use in high packing-density VLSI CMOS circuits is examined. It is shown that full vertical isolation can be maintained even when the well beneath a p** plus diffusion is completely depleted - that is, the p** plus -to-n-well and n-well-to-p-substrate depletion regions meet - and that this offers an advantage in terms of p** plus junction capacitance. However, if thin p-on-p** plus epitaxial substrate material is used for latch-up suppression, then vertical isolation can be severely degraded. This effect ultimately limits the thickness of the epitaxial layer and hence the degree of latch-up protection.

Original languageEnglish
Pages (from-to)107-109
Number of pages3
JournalElectron device letters
VolumeEDL-8
Issue number3
DOIs
Publication statusPublished - 1987

ASJC Scopus subject areas

  • Engineering(all)

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