TY - GEN
T1 - Vertical 3D NAND flash memory technology
AU - Nitayama, Akihiro
AU - Aochi, Hideaki
PY - 2011
Y1 - 2011
N2 - We've developed Bit Cost Scalable (BiCS) flash technology as a three-dimensional memory for the future ultra high density storage devices, which extremely reduces the chip costs by vertically stacking memory arrays with punch and plug process. We've advanced it into Pipe-shaped BiCS flash memory introducing U-shaped NAND string structure, to improve operation window, speed and reliability. 32 G bit test chips with 16 stacked layers by 60nm P-BiCS flash process have been fabricated, and the functionality of Multi-Level-Cell (MLC) operation has been successfully demonstrated. P-BiCS is the most promising candidate of three-dimensional ultra high density data storage memories.
AB - We've developed Bit Cost Scalable (BiCS) flash technology as a three-dimensional memory for the future ultra high density storage devices, which extremely reduces the chip costs by vertically stacking memory arrays with punch and plug process. We've advanced it into Pipe-shaped BiCS flash memory introducing U-shaped NAND string structure, to improve operation window, speed and reliability. 32 G bit test chips with 16 stacked layers by 60nm P-BiCS flash process have been fabricated, and the functionality of Multi-Level-Cell (MLC) operation has been successfully demonstrated. P-BiCS is the most promising candidate of three-dimensional ultra high density data storage memories.
UR - http://www.scopus.com/inward/record.url?scp=84857308038&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84857308038&partnerID=8YFLogxK
U2 - 10.1149/1.3633282
DO - 10.1149/1.3633282
M3 - Conference contribution
AN - SCOPUS:84857308038
SN - 9781566779074
T3 - ECS Transactions
SP - 15
EP - 25
BT - ULSI Process Integration 7
PB - Electrochemical Society Inc.
T2 - 7th Symposium on ULSI Process Integration - 220th ECS Meeting
Y2 - 9 October 2011 through 14 October 2011
ER -