Variability analysis of scaled poly-Si channel FinFETs and tri-gate flash memories for high density and low cost stacked 3D-memory application

Y. X. Liu, T. Mastukawa, K. Endo, S. O'uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, K. Sakamoto, M. Masahara, T. Kamei, T. Hayashida, A. Ogura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The threshold voltage (Vt) in scaled poly-Si channel FinFETs and tri-gate flash memories with poly-Si floating gate (FG) was systematically compared with crystal channel ones, for the first time. It was found that some superior Id-Vg characteristics are observed in the scaled poly-Si channel FinFETs with gate length (Lg) down to 54 nm or less. The standard deviation of Vt (σVt) of poly-Si channel FinFETs was 3 times higher than that of crystal channel ones at the same gate oxide thickness (Tox). However, the σVt of poly-Si channel tri-gate flash memories after one program/erase (P/E) cycle became comparable to that of crystal channel ones. Moreover, it was found that punch-through voltage of the poly-Si channel tri-gate flash memory is as high as 4.6 V even Lg was down to 76 nm.

Original languageEnglish
Title of host publicationESSDERC 2011 - Proceedings of the 41st European Solid-State Device Research Conference
Pages203-206
Number of pages4
DOIs
Publication statusPublished - 2011 Dec 12
Externally publishedYes
Event41st European Solid-State Device Research Conference, ESSDERC 2011 - Helsinki, Finland
Duration: 2011 Sep 122011 Sep 16

Publication series

NameEuropean Solid-State Device Research Conference
ISSN (Print)1930-8876

Other

Other41st European Solid-State Device Research Conference, ESSDERC 2011
CountryFinland
CityHelsinki
Period11/9/1211/9/16

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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