In this paper, by combining conventional spin coating method with vacuum treatment, a relatively simple and feasible process technique referred to as vacuum-assisted spin coating technique was proposed to get uniform polyimide liner along sidewalls of high aspect ratio Through-Silicon-Vias (TSVs) for three-dimensional (3D) integration applications. Details about the proposed technique were illustrated and test structures of silicon blind vias with diameter of about 6μm and depth of about 51μm were successfully sidewall coated with polyimide liner with step coverage around 30% utilizing the technique proposed. For thermal reliability investigations of the cured polyimide liner, X-ray photoelectron spectroscopy (XPS) analysis was performed to get the chemical state information of the cured polyimide liner. Also, planar metal-insulator-semiconductor (MIS) capacitor which involves polyimide as insulator was built to investigate electrical properties of polyimide liner formed. Electrical characteristics such as capacitance-voltage(C-V) curve and leakage current under biased voltage up to 20V were measured. All these results showed the potential of the technique proposed to be applied to high aspect ratio TSVs for 3D integration.