Universal VLSI based on a redundant multiple-valued sequential logic operation

Tasuku Ito, Michitaka Kameyama

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


In the next-generation VLSI, it is desired to achieve ultimate flexibility and a high-performance low-power operation equivalent to that of a fullcustom VLSI. In this paper, a reconfigurable VLSI which realizes a high-performance sequential logic circuit based on a bit-serial operation is proposed. A universal sequential logic module (USLM) suitable for local data transfer in a programmed sequential logic circuit is presented. A redundant multiple-valued sequential logic operation is also proposed, where linear summation of time-by-time adjacent bits is fully utilized to increase the input/output throughput of a sequential logic circuit. Moreover, packet data transfer scheme is introduced to make programmable interconnection possible in the bit-serial data transfer between cells composed of the multiple USLMs.

Original languageEnglish
Pages (from-to)553-567
Number of pages15
JournalJournal of Multiple-Valued Logic and Soft Computing
Issue number4-6
Publication statusPublished - 2007 Nov 29


  • Bit-serial arithmetic and logic operation
  • Intrachip packet data transfer
  • Multiple-valued logic operation
  • Reconfigurable VLSI
  • Sequential logic circuit

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Logic


Dive into the research topics of 'Universal VLSI based on a redundant multiple-valued sequential logic operation'. Together they form a unique fingerprint.

Cite this