Abstract
In the next-generation VLSI, it is desired to achieve ultimate flexibility and a high-performance low-power operation equivalent to that of a fullcustom VLSI. In this paper, a reconfigurable VLSI which realizes a high-performance sequential logic circuit based on a bit-serial operation is proposed. A universal sequential logic module (USLM) suitable for local data transfer in a programmed sequential logic circuit is presented. A redundant multiple-valued sequential logic operation is also proposed, where linear summation of time-by-time adjacent bits is fully utilized to increase the input/output throughput of a sequential logic circuit. Moreover, packet data transfer scheme is introduced to make programmable interconnection possible in the bit-serial data transfer between cells composed of the multiple USLMs.
Original language | English |
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Pages (from-to) | 553-567 |
Number of pages | 15 |
Journal | Journal of Multiple-Valued Logic and Soft Computing |
Volume | 13 |
Issue number | 4-6 |
Publication status | Published - 2007 Nov 29 |
Keywords
- Bit-serial arithmetic and logic operation
- Intrachip packet data transfer
- Multiple-valued logic operation
- Reconfigurable VLSI
- Sequential logic circuit
ASJC Scopus subject areas
- Software
- Theoretical Computer Science
- Logic