Universal VLSI based on a redundant multiple-valued sequential logic operation

Tasuku Ito, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In the next-generation VLSI, it is desired to achieve ultimate flexibility and a high-performance low-power operation equivalent to that of a full-custom VLSI. In this paper, a reconfigurable VLSI which realizes a high-performance sequential logic circuit based on a bit-serial operation is proposed. A universal sequential logic module (USLM) suitable for local data transfer in a programmed sequential logic circuit is presented. A redundant multiple-valued sequential logic operation is also proposed, where linear summation of time-by-time adjacent bits is fully utilized to increase the input/output throughput of a sequential logic circuit. Moreover, packet data transfer scheme is introduced to make programmable interconnection possible in the bit-serial data transfer between cells composed of the multiple USLMs.

Original languageEnglish
Title of host publication37th International Symposium on Multiple-Valued Logic, ISMVL 2007
DOIs
Publication statusPublished - 2007 Sep 3
Event37th International Symposium on Multiple-Valued Logic, ISMVL 2007 - Oslo, Norway
Duration: 2007 May 132007 May 16

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other37th International Symposium on Multiple-Valued Logic, ISMVL 2007
CountryNorway
CityOslo
Period07/5/1307/5/16

ASJC Scopus subject areas

  • Hardware and Architecture
  • Logic
  • Safety, Risk, Reliability and Quality
  • Chemical Health and Safety

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