Unified scheduling of high performance parallel VLSI processors for robotics

Bumchul Kim, Michitaka Kameyama, Tatsuo Higuchi

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

The performance of processing elements can be improved by the progress of VLSI circuit technology, while the communication overhead can not be negligible in parallel processing system. This paper presents a unified scheduling that allocates tasks having processing times in multiple processing elements. The objective function is formulated to measure communication time between processing elements. By employing constraints conditions, the scheduling efficiently generates an optimal solution using a integer programming so that minimum communication time can be achieved. We also propose a VLSI processor for robotics whose latency is very small. In the VLSI processor, the data transfer between two processing elements can be done very quickly, so that the communication cycle time is greatly reduced.

Original languageEnglish
Pages (from-to)904-910
Number of pages7
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE76-A
Issue number6
Publication statusPublished - 1993 Jun 1

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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