Ultralow-power TFT with gate oxide fabricated by nitric acid oxidation method

Taketoshi Matsumoto, Yasushi Kubota, Mikihiro Yamada, Hiroshi Tsuji, Takafumi Shimatani, Yasuhiro Hirayama, Sumio Terakawa, Shigeki Imai, Hikaru Kobayashi

Research output: Contribution to journalArticlepeer-review

8 Citations (Scopus)

Abstract

We have fabricated a thin-film transistor (TFT) in which a gate oxide layer possesses a stack structure with an ultrathin interfacial SiO2 layer formed by the nitric acid oxidation of silicon (NAOS) method at room temperature and a 40 nm CVD SiO2 layer. The drain currentvoltage characteristics show that TFT with NAOS interfacial layer can be operated at 3 V (the conventional operation voltage is 1215 V), indicating that a vast decrease in TFT power consumption is possible. The threshold voltage becomes less than 1 V, and the short-channel effect can be avoided.

Original languageEnglish
Article number5491087
Pages (from-to)821-823
Number of pages3
JournalIEEE Electron Device Letters
Volume31
Issue number8
DOIs
Publication statusPublished - 2010 Aug
Externally publishedYes

Keywords

  • Dielectric films
  • leakage currents
  • oxidation
  • thin-film transistor (TFT)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Ultralow-power TFT with gate oxide fabricated by nitric acid oxidation method'. Together they form a unique fingerprint.

Cite this