Ultralow-power TFT with gate oxide fabricated by nitric acid oxidation method

Taketoshi Matsumoto; Yasushi Kubota; Mikihiro Yamada; Hiroshi Tsuji; Takafumi Shimatani; Yasuhiro Hirayama; Sumio Terakawa; Shigeki Imai; Hikaru Kobayashi

doi:10.1109/LED.2010.2050856

Ultralow-power TFT with gate oxide fabricated by nitric acid oxidation method

Taketoshi Matsumoto, Yasushi Kubota, Mikihiro Yamada, Hiroshi Tsuji, Takafumi Shimatani, Yasuhiro Hirayama, Sumio Terakawa, Shigeki Imai, Hikaru Kobayashi

Research output: Contribution to journal › Article › peer-review

8 Citations (Scopus)

Abstract

We have fabricated a thin-film transistor (TFT) in which a gate oxide layer possesses a stack structure with an ultrathin interfacial SiO₂ layer formed by the nitric acid oxidation of silicon (NAOS) method at room temperature and a 40 nm CVD SiO₂ layer. The drain currentvoltage characteristics show that TFT with NAOS interfacial layer can be operated at 3 V (the conventional operation voltage is 1215 V), indicating that a vast decrease in TFT power consumption is possible. The threshold voltage becomes less than 1 V, and the short-channel effect can be avoided.

Original language	English
Article number	5491087
Pages (from-to)	821-823
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	31
Issue number	8
DOIs	https://doi.org/10.1109/LED.2010.2050856
Publication status	Published - 2010 Aug
Externally published	Yes

Keywords

Dielectric films
leakage currents
oxidation
thin-film transistor (TFT)

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/LED.2010.2050856

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Ultralow-power TFT with gate oxide fabricated by nitric acid oxidation method. / Matsumoto, Taketoshi; Kubota, Yasushi; Yamada, Mikihiro; Tsuji, Hiroshi; Shimatani, Takafumi; Hirayama, Yasuhiro; Terakawa, Sumio; Imai, Shigeki; Kobayashi, Hikaru.

In: IEEE Electron Device Letters, Vol. 31, No. 8, 5491087, 08.2010, p. 821-823.

Research output: Contribution to journal › Article › peer-review

@article{0c82f9c21c0d4fedb270efac1b0cb806,

title = "Ultralow-power TFT with gate oxide fabricated by nitric acid oxidation method",

abstract = "We have fabricated a thin-film transistor (TFT) in which a gate oxide layer possesses a stack structure with an ultrathin interfacial SiO2 layer formed by the nitric acid oxidation of silicon (NAOS) method at room temperature and a 40 nm CVD SiO2 layer. The drain currentvoltage characteristics show that TFT with NAOS interfacial layer can be operated at 3 V (the conventional operation voltage is 1215 V), indicating that a vast decrease in TFT power consumption is possible. The threshold voltage becomes less than 1 V, and the short-channel effect can be avoided.",

keywords = "Dielectric films, leakage currents, oxidation, thin-film transistor (TFT)",

author = "Taketoshi Matsumoto and Yasushi Kubota and Mikihiro Yamada and Hiroshi Tsuji and Takafumi Shimatani and Yasuhiro Hirayama and Sumio Terakawa and Shigeki Imai and Hikaru Kobayashi",

year = "2010",

month = aug,

doi = "10.1109/LED.2010.2050856",

language = "English",

volume = "31",

pages = "821--823",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "8",

}

TY - JOUR

T1 - Ultralow-power TFT with gate oxide fabricated by nitric acid oxidation method

AU - Matsumoto, Taketoshi

AU - Kubota, Yasushi

AU - Yamada, Mikihiro

AU - Tsuji, Hiroshi

AU - Shimatani, Takafumi

AU - Hirayama, Yasuhiro

AU - Terakawa, Sumio

AU - Imai, Shigeki

AU - Kobayashi, Hikaru

PY - 2010/8

Y1 - 2010/8

N2 - We have fabricated a thin-film transistor (TFT) in which a gate oxide layer possesses a stack structure with an ultrathin interfacial SiO2 layer formed by the nitric acid oxidation of silicon (NAOS) method at room temperature and a 40 nm CVD SiO2 layer. The drain currentvoltage characteristics show that TFT with NAOS interfacial layer can be operated at 3 V (the conventional operation voltage is 1215 V), indicating that a vast decrease in TFT power consumption is possible. The threshold voltage becomes less than 1 V, and the short-channel effect can be avoided.

AB - We have fabricated a thin-film transistor (TFT) in which a gate oxide layer possesses a stack structure with an ultrathin interfacial SiO2 layer formed by the nitric acid oxidation of silicon (NAOS) method at room temperature and a 40 nm CVD SiO2 layer. The drain currentvoltage characteristics show that TFT with NAOS interfacial layer can be operated at 3 V (the conventional operation voltage is 1215 V), indicating that a vast decrease in TFT power consumption is possible. The threshold voltage becomes less than 1 V, and the short-channel effect can be avoided.

KW - Dielectric films

KW - leakage currents

KW - oxidation

KW - thin-film transistor (TFT)

UR - http://www.scopus.com/inward/record.url?scp=77955175619&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77955175619&partnerID=8YFLogxK

U2 - 10.1109/LED.2010.2050856

DO - 10.1109/LED.2010.2050856

M3 - Article

AN - SCOPUS:77955175619

VL - 31

SP - 821

EP - 823

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 8

M1 - 5491087

ER -

Ultralow-power TFT with gate oxide fabricated by nitric acid oxidation method

Abstract

Keywords

ASJC Scopus subject areas

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