Abstract
We have fabricated a thin-film transistor (TFT) in which a gate oxide layer possesses a stack structure with an ultrathin interfacial SiO2 layer formed by the nitric acid oxidation of silicon (NAOS) method at room temperature and a 40 nm CVD SiO2 layer. The drain currentvoltage characteristics show that TFT with NAOS interfacial layer can be operated at 3 V (the conventional operation voltage is 1215 V), indicating that a vast decrease in TFT power consumption is possible. The threshold voltage becomes less than 1 V, and the short-channel effect can be avoided.
Original language | English |
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Article number | 5491087 |
Pages (from-to) | 821-823 |
Number of pages | 3 |
Journal | IEEE Electron Device Letters |
Volume | 31 |
Issue number | 8 |
DOIs | |
Publication status | Published - 2010 Aug |
Externally published | Yes |
Keywords
- Dielectric films
- leakage currents
- oxidation
- thin-film transistor (TFT)
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering