Ultrafast Operation of Vth-Adjusted P+ -n+ Double-Gate SOI MOSFET's

Tetsu Tanaka, Kunihiro Suzuki, Hiroshi Horie, Toshihiro Sugii

Research output: Contribution to journalArticlepeer-review

69 Citations (Scopus)


To optimize the Vthof double-gate SOI MOSFET's, we fabricated devices with p+poly-Si for the fæntgate electrode and n+poly-Si for the back-gate electrode on 40-nm-thick directbonded SOI wafers. We obtained an experimental Vth of 0.17 V for nMOS and -0.24 V for pMOS devices. These double-gate devices have good short-channel characteristics, low parasitic resistances, and large drive currents. For gates 0.19 µm long, front-gate oxides 8.2 nm thick, and back-gate oxides 9.9 nm thick, we obtained ring oscillator delay times of 43 ps at 1 V and 27 ps at 2 V. To our knowledge, these values are the fastest reported for this gate length with suppressed short-channel effects.

Original languageEnglish
Pages (from-to)386-388
Number of pages3
JournalIEEE Electron Device Letters
Issue number10
Publication statusPublished - 1994 Oct
Externally publishedYes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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