Abstract
In this study, p+-n+ double-gate SOI MOSFET's have been fabricated using direct bonded SOI wafers just 40 nm thick. These devices, with an appropriate Vth, have good short-channel behavior and a large drive current. Obtained is an inverter delay time of 43 ps at 1 V, and 27 ps at 2 V, for Lg = 0.19 μm. These are the fastest reported values for this gate length.
Original language | English |
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Pages (from-to) | 11-12 |
Number of pages | 2 |
Journal | Digest of Technical Papers - Symposium on VLSI Technology |
Publication status | Published - 1994 Dec 1 |
Externally published | Yes |
Event | Proceedings of the 1994 Symposium on VLSI Technology - Honolulu, HI, USA Duration: 1994 Jun 7 → 1994 Jun 9 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering