Ultrafast low-power operation of p+-n+ double-gate SOI MOSFETs

Tetsu Tanaka; Kunihiro Suzuki; Hiroshi Horie; Toshihiro Sugii

Ultrafast low-power operation of p⁺-n⁺ double-gate SOI MOSFETs

Tetsu Tanaka, Kunihiro Suzuki, Hiroshi Horie, Toshihiro Sugii

Research output: Contribution to journal › Conference article

Abstract

In this study, p⁺-n⁺ double-gate SOI MOSFET's have been fabricated using direct bonded SOI wafers just 40 nm thick. These devices, with an appropriate V_th, have good short-channel behavior and a large drive current. Obtained is an inverter delay time of 43 ps at 1 V, and 27 ps at 2 V, for Lg = 0.19 μm. These are the fastest reported values for this gate length.

Original language	English
Pages (from-to)	11-12
Number of pages	2
Journal	Digest of Technical Papers - Symposium on VLSI Technology
Publication status	Published - 1994 Dec 1
Externally published	Yes
Event	Proceedings of the 1994 Symposium on VLSI Technology - Honolulu, HI, USA Duration: 1994 Jun 7 → 1994 Jun 9

ASJC Scopus subject areas

Electrical and Electronic Engineering

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Tanaka, T., Suzuki, K., Horie, H., & Sugii, T. (1994). Ultrafast low-power operation of p⁺-n⁺ double-gate SOI MOSFETs. Digest of Technical Papers - Symposium on VLSI Technology, 11-12.

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abstract = "In this study, p+-n+ double-gate SOI MOSFET's have been fabricated using direct bonded SOI wafers just 40 nm thick. These devices, with an appropriate Vth, have good short-channel behavior and a large drive current. Obtained is an inverter delay time of 43 ps at 1 V, and 27 ps at 2 V, for Lg = 0.19 μm. These are the fastest reported values for this gate length.",

author = "Tetsu Tanaka and Kunihiro Suzuki and Hiroshi Horie and Toshihiro Sugii",

year = "1994",

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AU - Tanaka, Tetsu

AU - Suzuki, Kunihiro

AU - Horie, Hiroshi

AU - Sugii, Toshihiro

PY - 1994/12/1

Y1 - 1994/12/1

N2 - In this study, p+-n+ double-gate SOI MOSFET's have been fabricated using direct bonded SOI wafers just 40 nm thick. These devices, with an appropriate Vth, have good short-channel behavior and a large drive current. Obtained is an inverter delay time of 43 ps at 1 V, and 27 ps at 2 V, for Lg = 0.19 μm. These are the fastest reported values for this gate length.

AB - In this study, p+-n+ double-gate SOI MOSFET's have been fabricated using direct bonded SOI wafers just 40 nm thick. These devices, with an appropriate Vth, have good short-channel behavior and a large drive current. Obtained is an inverter delay time of 43 ps at 1 V, and 27 ps at 2 V, for Lg = 0.19 μm. These are the fastest reported values for this gate length.

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