Abstract
A source and drain junction technology is proposed for realizing sub 0.1 μm NMOSFETs. In this technology, source and drain extension (SDE) is fabricated using As diffusion from As absorbed atomic layer on silicon surface by high temperature RTA. NMOSFET fabricated using this technology shows better suppression of short channel effect (SCE) compared to conventional FET.
Original language | English |
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Pages | 80-81 |
Number of pages | 2 |
Publication status | Published - 1999 |
Event | Proceedings of the 1999 57th Annual Device Research Conference Digest (DRC) - Santa Barbara, CA, USA Duration: 1999 Jun 28 → 1999 Jun 30 |
Other
Other | Proceedings of the 1999 57th Annual Device Research Conference Digest (DRC) |
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City | Santa Barbara, CA, USA |
Period | 99/6/28 → 99/6/30 |
ASJC Scopus subject areas
- Engineering(all)