Ultra-low series resistance W/ErSi2/n+-Si and W/Pd2Si/p+-Si S/D electrodes for advanced CMOS platform

Rihito Kuroda, Hiroaki Tanaka, Yukihisa Nakao, Akinobu Teramoto, Naoto Miyamoto, Shigetoshi Sugawa, Tadahiro Ohmi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

A formation technology of ultra-low series resistance CMOS source/drain (S/D) electrodes is developed. The silicide/silicon contact resistivity (R c) of 8.0×10-10 Ω·cm2 and the electrode's sheet resistance (Rsheet) of less than 5.0 Ω/□ are achieved for both n- and pMOS using W/ErSi2 and W/Pd2Si metal stacked silicide structures. For the first time, FD-SOI CMOS with the developed S/D electrodes was fabricated and the ring oscillator speed performance was evaluated.

Original languageEnglish
Title of host publication2010 IEEE International Electron Devices Meeting, IEDM 2010
Pages26.2.1-26.2.4
DOIs
Publication statusPublished - 2010 Dec 1
Event2010 IEEE International Electron Devices Meeting, IEDM 2010 - San Francisco, CA, United States
Duration: 2010 Dec 62010 Dec 8

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Other

Other2010 IEEE International Electron Devices Meeting, IEDM 2010
CountryUnited States
CitySan Francisco, CA
Period10/12/610/12/8

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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    Kuroda, R., Tanaka, H., Nakao, Y., Teramoto, A., Miyamoto, N., Sugawa, S., & Ohmi, T. (2010). Ultra-low series resistance W/ErSi2/n+-Si and W/Pd2Si/p+-Si S/D electrodes for advanced CMOS platform. In 2010 IEEE International Electron Devices Meeting, IEDM 2010 (pp. 26.2.1-26.2.4). [5703425] (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2010.5703425