Ultra-highly parallel residue arithmetic VLSI system

Michitaka Kameyama, Tsutomu Sekibe, Tatsuo Higuchi

Research output: Contribution to conferencePaperpeer-review

Abstract

The authors present a novel multiple-valued residue arithmetic VLSI system. The multiple-valued residue digit coding based on the pseudo-primitive root permits highly parallel arithmetic operations. Furthermore, these circuits can be effectively implemented through the use of the multiple-valued bidirectional current-mode circuits. As a result, an ultrahigh-speed arithmetic VLSI system can be realized because of its high degree of parallelism. In the proposed residue arithmetic circuit, three-operand multiplication-addition can always be performed within a fixed delay time of the module because of its high degree of parallelism. Furthermore, the hardware complexity is greatly reduced due to the regularity of the structure and the use of multiple-valued logic.

Original languageEnglish
Pages127-128
Number of pages2
Publication statusPublished - 1989 Dec 1
EventSymposium on VLSI Circuits 1989 - Kyoto, Japan
Duration: 1989 May 251989 May 27

Other

OtherSymposium on VLSI Circuits 1989
CityKyoto, Japan
Period89/5/2589/5/27

ASJC Scopus subject areas

  • Engineering(all)

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