A novel distributed digital selector circuit is proposed. The circuit comprises eight stages of series-gated source coupled FET logic (SCFL) selector cell units, and can be directly connected to an SCFL interface. The integrated circuit (IC) fabricated with 0.16μm GaAs MESFETs exhibited clear eye-openings at 70Gbit/ s, a much higher bit rate than that of conventional selector ICs based on a lumped-element circuit design.
ASJC Scopus subject areas
- Electrical and Electronic Engineering