Abstract
A novel two-dimensional device simulator for poly-Si TFTs (thin-film transistors) is developed, in which the effects of grain boundaries (GBs) are incorporated into the carrier mobility model. In this simulator, the basic semiconductor equations are iteratively solved in combination with the carrier generation/recombination model, which consists of avalanche, S-R-H, and Auger processes. By using this simulator, the effects of GBs on device characteristics are accurately evaluated. In addition, the avalanche-induced short channel effect in poly-Si TFTs is numerically analyzed.
| Original language | English |
|---|---|
| Pages (from-to) | 859-862 |
| Number of pages | 4 |
| Journal | Technical Digest - International Electron Devices Meeting |
| Publication status | Published - 1990 Dec 1 |
| Event | 1990 International Electron Devices Meeting - San Francisco, CA, USA Duration: 1990 Dec 9 → 1990 Dec 12 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry
Fingerprint Dive into the research topics of 'Two-dimensional device simulation for avalanche induced short channel effect in poly-Si TFT'. Together they form a unique fingerprint.
Cite this
Yamada, S., Yokoyama, S., & Koyanagi, M. (1990). Two-dimensional device simulation for avalanche induced short channel effect in poly-Si TFT. Technical Digest - International Electron Devices Meeting, 859-862.