Tunneling barrier engineered charge trap flash memory with ONO and NON tunneling dielectric layers

Goon Ho Park, Myung Ho Jung, Kwan Su Kim, Hong Bay Chung, Won Ju Cho

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)

Abstract

Tunneling barrier engineered charge trap flash (TBE-CTF) memory devices were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin SiO2 and Si3N4 dielectric layers were used as engineered tunneling barrier. A faster program/erase speed as well as a larger memory window was achieved from the TBE-CTF memory. The VARIOT-type tunneling barrier composed of oxide-nitride-oxide (ONO) layers revealed a longer retention time and superior endurance characteristic. On the other hand, the CRESTED tunneling barrier composed of nitride-oxide-nitride (NON) layers showed degraded retention and endurance characteristics. It is found that the degradation of NON barrier is associated with the increase of interface state density at the tunneling barrier/silicon channel by programming and erasing (P/E) stress.

Original languageEnglish
Pages (from-to)e13-e17
JournalCurrent Applied Physics
Volume10
Issue number1 SUPPL. 1
DOIs
Publication statusPublished - 2010 Jan
Externally publishedYes

Keywords

  • CRESTED
  • Charge trap flash
  • Interface trap density
  • Tunnel barrier engineering
  • VARIOT

ASJC Scopus subject areas

  • Materials Science(all)
  • Physics and Astronomy(all)

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