Tunnel FinFET CMOS inverter with very low short-circuit current for ultralow-power Internet of Things application

Yukinori Morita, Koichi Fukuda, Yongxun Liu, Takahiro Mori, Wataru Mizubayashi, Shin Ichi O'Uchi, Hiroshi Fuketa, Shintaro Otsuka, Shinji Migita, Meishoku Masahara, Kazuhiko Endo, Hiroyuki Ota, Takashi Matsukawa

Research output: Contribution to journalArticlepeer-review

8 Citations (Scopus)

Abstract

We have demonstrated the operation of a CMOS inverter consisting of Si tunnel FinFETs. Both p- and n-type tunnel FinFETs are successfully fabricated and operated on the same SOI wafer. The current mismatch between p- and n-type tunnel FETs is compensated by tuning the number of fin channels. Very low short-circuit current and clear voltage input-output characteristics are obtained. The thin epitaxial channel in the tunnel FinFETs effectively increases the drain current and accordingly reduces the drain capacitance, which could help high-performance tunnel FET CMOS inverter operation.

Original languageEnglish
Article number04CD19
JournalJapanese journal of applied physics
Volume56
Issue number4
DOIs
Publication statusPublished - 2017 Apr 1
Externally publishedYes

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

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