Transistor on capacitor (TOC) cell with quarter pitch layout for 0.13 μm DRAMs and beyond

M. Sato, S. Ishibashi, T. Kajiyama, M. Sakuma, I. Mizushima, Y. Tsunashima, F. Shoji, H. Yano, A. Nitayama, T. Hamamoto

Research output: Contribution to journalConference articlepeer-review

2 Citations (Scopus)

Abstract

We present a new trench type cell, transistor on capacitor (TOC) cell with 1/4 pitch layout. Two kinds of new idea have been implemented. One is that the density of the trench capacitor is closest packed by introducing 1/4 pitch layout. The other is that the transfer transistor is fabricated over the trench capacitor by introducing the newly developed epitaxial growth and Chemical Mechanical Polish (CMP) technologies. As a result, trench opening can be enlarged without reducing the gate length of the transfer transistor.

Original languageEnglish
Pages (from-to)82-83
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
Publication statusPublished - 2000
Event2000 Symposium on VLSI Technology - Honolulu, HI, USA
Duration: 2000 Jun 132000 Jun 15

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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