Timing-variation-aware multiple-valued current-mode circuit for a low-power pipelined system

Takashi Matsuura, Hirokatsu Shirahama, Masanori Natsui, Takahiro Hanyu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

A dynamic current-source control technique in multiplevalued current-mode (MVCM) circuits is proposed for a power-aware pipelined system. An output monitor in each pipeline stage detects that the combinational logic block has completed a computation for a particular piece of input data and its result has been stored into the pipeline register, and generates "operation- completion" signal. All the current sources in the pipeline stage are cut off by using this control signal. The use of this current-source control technique makes it possible to completely eliminate wasted steady current flow during the rest of clock period, which greedily reduces the power dissipation with maintaining the operating frequency. The efficiency of the proposed technique in a simpleMVCMcircuit is confirmed using HSPICE simulation under 90nm CMOS. The power dissipation of the MVCM circuit using the proposed technique is always less than that of a corresponding CMOS implementation at the operating frequency of 0.8GHz and more.

Original languageEnglish
Title of host publicationProceedings - 39th International Symposium on Multiple-Valued Logic, ISMVL 2009
Pages60-65
Number of pages6
DOIs
Publication statusPublished - 2009 Sep 30
Event39th International Symposium on Multiple-Valued Logic, ISMVL 2009 - Naha, Okinawa, Japan
Duration: 2009 May 212009 May 23

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other39th International Symposium on Multiple-Valued Logic, ISMVL 2009
CountryJapan
CityNaha, Okinawa
Period09/5/2109/5/23

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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