Timing-variation-aware multiple-valued current-mode circuit for a low-power pipelined system

A dynamic current-source control technique in multiplevalued current-mode (MVCM) circuits is proposed for a power-aware pipelined system. An output monitor in each pipeline stage detects that the combinational logic block has completed a computation for a particular piece of input data and its result has been stored into the pipeline register, and generates "operation- completion" signal. All the current sources in the pipeline stage are cut off by using this control signal. The use of this current-source control technique makes it possible to completely eliminate wasted steady current flow during the rest of clock period, which greedily reduces the power dissipation with maintaining the operating frequency. The efficiency of the proposed technique in a simpleMVCMcircuit is confirmed using HSPICE simulation under 90nm CMOS. The power dissipation of the MVCM circuit using the proposed technique is always less than that of a corresponding CMOS implementation at the operating frequency of 0.8GHz and more.