Timing optimization on mapped circuits

Ko Yoshikawa, Hiroshi Ichiryu, Hisato Tanishita, Sigenobu Suzuki, Nobuyoshi Nomizu, Akira Kondoh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Techniques for timing optimization of CMOS or BiCMOS gate array or standard cell circuits are presented. Based on previous works on critical path resynthesis, technology mapping algorithms using dynamic programming techniques, and fanout optimization algorithms, the following techniques were developed: a hierarchical data structure in which a circuit is partitioned into subcircuits, a weight function to gate subcircuits in terms of their potential for delay reduction, a critical path resynthesis technique preceded by noncritical path resynthesis, a mapping algorithm using tree covering techniques tightly coupled with a fanout optimization algorithm which can treat dual signals not only in sinks but also in sources, and a correction procedure for short paths. A program using these techniques achieves an average speedup of 37% with 27% increase in area on the DAC'86 benchmark set plus several additional circuits from actual designs.

Original languageEnglish
Title of host publicationProceedings - Design Automation Conference
PublisherPubl by IEEE
Pages112-117
Number of pages6
ISBN (Print)0818691492, 9780818691492
DOIs
Publication statusPublished - 1991
Externally publishedYes
EventProceedings of the 28th ACM/IEEE Design Automation Conference - San Francisco, CA, USA
Duration: 1991 Jun 171991 Jun 21

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0146-7123

Conference

ConferenceProceedings of the 28th ACM/IEEE Design Automation Conference
CitySan Francisco, CA, USA
Period91/6/1791/6/21

ASJC Scopus subject areas

  • Engineering(all)

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