Timing optimization on mapped circuits

Techniques for timing optimization of CMOS or BiCMOS gate array or standard cell circuits are presented. Based on previous works on critical path resynthesis, technology mapping algorithms using dynamic programming techniques, and fanout optimization algorithms, the following techniques were developed: a hierarchical data structure in which a circuit is partitioned into subcircuits, a weight function to gate subcircuits in terms of their potential for delay reduction, a critical path resynthesis technique preceded by noncritical path resynthesis, a mapping algorithm using tree covering techniques tightly coupled with a fanout optimization algorithm which can treat dual signals not only in sinks but also in sources, and a correction procedure for short paths. A program using these techniques achieves an average speedup of 37% with 27% increase in area on the DAC'86 benchmark set plus several additional circuits from actual designs.