TY - GEN
T1 - Timing optimization on mapped circuits
AU - Yoshikawa, Ko
AU - Ichiryu, Hiroshi
AU - Tanishita, Hisato
AU - Suzuki, Sigenobu
AU - Nomizu, Nobuyoshi
AU - Kondoh, Akira
PY - 1991
Y1 - 1991
N2 - Techniques for timing optimization of CMOS or BiCMOS gate array or standard cell circuits are presented. Based on previous works on critical path resynthesis, technology mapping algorithms using dynamic programming techniques, and fanout optimization algorithms, the following techniques were developed: a hierarchical data structure in which a circuit is partitioned into subcircuits, a weight function to gate subcircuits in terms of their potential for delay reduction, a critical path resynthesis technique preceded by noncritical path resynthesis, a mapping algorithm using tree covering techniques tightly coupled with a fanout optimization algorithm which can treat dual signals not only in sinks but also in sources, and a correction procedure for short paths. A program using these techniques achieves an average speedup of 37% with 27% increase in area on the DAC'86 benchmark set plus several additional circuits from actual designs.
AB - Techniques for timing optimization of CMOS or BiCMOS gate array or standard cell circuits are presented. Based on previous works on critical path resynthesis, technology mapping algorithms using dynamic programming techniques, and fanout optimization algorithms, the following techniques were developed: a hierarchical data structure in which a circuit is partitioned into subcircuits, a weight function to gate subcircuits in terms of their potential for delay reduction, a critical path resynthesis technique preceded by noncritical path resynthesis, a mapping algorithm using tree covering techniques tightly coupled with a fanout optimization algorithm which can treat dual signals not only in sinks but also in sources, and a correction procedure for short paths. A program using these techniques achieves an average speedup of 37% with 27% increase in area on the DAC'86 benchmark set plus several additional circuits from actual designs.
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U2 - 10.1145/127601.127639
DO - 10.1145/127601.127639
M3 - Conference contribution
AN - SCOPUS:0026175349
SN - 0818691492
SN - 9780818691492
T3 - Proceedings - Design Automation Conference
SP - 112
EP - 117
BT - Proceedings - Design Automation Conference
PB - Publ by IEEE
T2 - Proceedings of the 28th ACM/IEEE Design Automation Conference
Y2 - 17 June 1991 through 21 June 1991
ER -