Timing optimization methodology based on replacing flip-flops by latches

Ko Yoshikawa, Keisuke Kanamaru, Yasuhiko Hagihara, Shigeto Inui, Yuichi Nakamura, Takeshi Yoshimura

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)

Abstract

Latch-based circuits have advantages for timing and are widely used for high-speed custom circuits. ASIC design flows, however, are based on circuits with flip-flops. This paper describes a new timing optimization algorithm by replacing the flip-flops in high-end ASICs by latches without changing the functionality of the circuits. Timing is optimized by using a fixed-phase retiming minimizing the impact of clock skew and jitter. A formal equivalence verification method that assures the logical correctness of the latch-replaced circuits is also proposed. Experimental results show that the optimization algorithm decreases the delay of benchmark circuits by as much as 17%.

Original languageEnglish
Pages (from-to)3151-3158
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE87-A
Issue number12
Publication statusPublished - 2004 Dec
Externally publishedYes

Keywords

  • Formal verification
  • Level-sensitive latch
  • Logic synthesis
  • Sequential circuit
  • Timing optimization

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

Fingerprint

Dive into the research topics of 'Timing optimization methodology based on replacing flip-flops by latches'. Together they form a unique fingerprint.

Cite this