Timing optimization methodology based on replacing flip-flops by latches

Ko Yoshikawa; Keisuke Kanamaru; Yasuhiko Hagihara; Shigeto Inui; Yuichi Nakamura; Takeshi Yoshimura

Timing optimization methodology based on replacing flip-flops by latches

Ko Yoshikawa, Keisuke Kanamaru, Yasuhiko Hagihara, Shigeto Inui, Yuichi Nakamura, Takeshi Yoshimura

Research output: Contribution to journal › Article › peer-review

Abstract

Latch-based circuits have advantages for timing and are widely used for high-speed custom circuits. ASIC design flows, however, are based on circuits with flip-flops. This paper describes a new timing optimization algorithm by replacing the flip-flops in high-end ASICs by latches without changing the functionality of the circuits. Timing is optimized by using a fixed-phase retiming minimizing the impact of clock skew and jitter. A formal equivalence verification method that assures the logical correctness of the latch-replaced circuits is also proposed. Experimental results show that the optimization algorithm decreases the delay of benchmark circuits by as much as 17%.

Original language	English
Pages (from-to)	3151-3158
Number of pages	8
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E87-A
Issue number	12
Publication status	Published - 2004 Dec
Externally published	Yes

Keywords

Formal verification
Level-sensitive latch
Logic synthesis
Sequential circuit
Timing optimization

ASJC Scopus subject areas

Signal Processing
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering
Applied Mathematics

Cite this

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abstract = "Latch-based circuits have advantages for timing and are widely used for high-speed custom circuits. ASIC design flows, however, are based on circuits with flip-flops. This paper describes a new timing optimization algorithm by replacing the flip-flops in high-end ASICs by latches without changing the functionality of the circuits. Timing is optimized by using a fixed-phase retiming minimizing the impact of clock skew and jitter. A formal equivalence verification method that assures the logical correctness of the latch-replaced circuits is also proposed. Experimental results show that the optimization algorithm decreases the delay of benchmark circuits by as much as 17%.",

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AU - Yoshikawa, Ko

AU - Kanamaru, Keisuke

AU - Hagihara, Yasuhiko

AU - Inui, Shigeto

AU - Nakamura, Yuichi

AU - Yoshimura, Takeshi

PY - 2004/12

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N2 - Latch-based circuits have advantages for timing and are widely used for high-speed custom circuits. ASIC design flows, however, are based on circuits with flip-flops. This paper describes a new timing optimization algorithm by replacing the flip-flops in high-end ASICs by latches without changing the functionality of the circuits. Timing is optimized by using a fixed-phase retiming minimizing the impact of clock skew and jitter. A formal equivalence verification method that assures the logical correctness of the latch-replaced circuits is also proposed. Experimental results show that the optimization algorithm decreases the delay of benchmark circuits by as much as 17%.

AB - Latch-based circuits have advantages for timing and are widely used for high-speed custom circuits. ASIC design flows, however, are based on circuits with flip-flops. This paper describes a new timing optimization algorithm by replacing the flip-flops in high-end ASICs by latches without changing the functionality of the circuits. Timing is optimized by using a fixed-phase retiming minimizing the impact of clock skew and jitter. A formal equivalence verification method that assures the logical correctness of the latch-replaced circuits is also proposed. Experimental results show that the optimization algorithm decreases the delay of benchmark circuits by as much as 17%.

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Timing optimization methodology based on replacing flip-flops by latches

Abstract

Keywords

ASJC Scopus subject areas

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