Time slot assignment algorithms to upstream links for decreasing transmission latency in IEEE 802.16j networks

Go Hasegawa, Shinpei Tanaka, Yoshiaki Taniguchi, Hirotaka Nakano

Research output: Contribution to journalArticlepeer-review

Abstract

In this paper, the authors focus on upstream transmission in TDMA-based IEEE 802.16j and propose two time slot assignment algorithms to decrease end-to-end transmission latency. One of the proposed algorithms assigns time slots considering the hop count from a gateway node, and the other takes the path from the relay node to the gateway node into account. In addition, a restriction in assigning time slots is introduced to reduce the delay at each relay node. The algorithms with the restriction assign later time slots considering the time slot order of links connecting a relay node. The performance of the proposed algorithms is evaluated through simulation experiments from the viewpoints of frame size and end-to-end transmission latency, and it is confirmed that the proposed algorithms achieve small transmission latency regardless of packet generation rate in the network, and decrease the transmission latency by up to 70% compared with the existing algorithm.

Original languageEnglish
Pages (from-to)1793-1801
Number of pages9
JournalIEICE Transactions on Communications
VolumeE95-B
Issue number5
DOIs
Publication statusPublished - 2012 May
Externally publishedYes

Keywords

  • End-to-end transmission latency
  • IEEE 802.16j
  • Time division multiple access (TDMA)
  • Time slot
  • Wireless multihop network

ASJC Scopus subject areas

  • Software
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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