Three-dimensional shared memory fabricated using wafer stacking technology

K. W. Lee, T. Nakamura, T. Ono, Y. Yamada, T. Mizukusa, H. Hashimoto, K. T. Park, H. Kurino, M. Koyanagi

Research output: Contribution to journalConference article

106 Citations (Scopus)

Abstract

We proposed a new three-dimensional (3D) shared memory for a high performance parallel processor system. In order to realize such new 3D shared memory, we have developed a new 3D integration technology based on the wafer stacking method. We fabricated the 3D shared memory test chip with three memory layers using our 3D integration technology. It was demonstrated that the basic memory operation and the broadcast operation of 3D shared memory are successfully performed.

Original languageEnglish
Pages (from-to)165-167
Number of pages3
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 2000 Dec 1
Event2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States
Duration: 2000 Dec 102000 Dec 13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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  • Cite this

    Lee, K. W., Nakamura, T., Ono, T., Yamada, Y., Mizukusa, T., Hashimoto, H., Park, K. T., Kurino, H., & Koyanagi, M. (2000). Three-dimensional shared memory fabricated using wafer stacking technology. Technical Digest - International Electron Devices Meeting, 165-167.