Abstract
We proposed a new three-dimensional (3D) shared memory for a high performance parallel processor system. In order to realize such new 3D shared memory, we have developed a new 3D integration technology based on the wafer stacking method. We fabricated the 3D shared memory test chip with three memory layers using our 3D integration technology. It was demonstrated that the basic memory operation and the broadcast operation of 3D shared memory are successfully performed.
| Original language | English |
|---|---|
| Pages (from-to) | 165-167 |
| Number of pages | 3 |
| Journal | Technical Digest - International Electron Devices Meeting |
| Publication status | Published - 2000 Dec 1 |
| Event | 2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States Duration: 2000 Dec 10 → 2000 Dec 13 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry
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Lee, K. W., Nakamura, T., Ono, T., Yamada, Y., Mizukusa, T., Hashimoto, H., Park, K. T., Kurino, H., & Koyanagi, M. (2000). Three-dimensional shared memory fabricated using wafer stacking technology. Technical Digest - International Electron Devices Meeting, 165-167.