Three-dimensional shared memory fabricated using wafer stacking technology

K. W. Lee; T. Nakamura; T. Ono; Y. Yamada; T. Mizukusa; H. Hashimoto; K. T. Park; H. Kurino; M. Koyanagi

Three-dimensional shared memory fabricated using wafer stacking technology

K. W. Lee, T. Nakamura, T. Ono, Y. Yamada, T. Mizukusa, H. Hashimoto, K. T. Park, H. Kurino, M. Koyanagi

Research output: Contribution to journal › Conference article › peer-review

Abstract

We proposed a new three-dimensional (3D) shared memory for a high performance parallel processor system. In order to realize such new 3D shared memory, we have developed a new 3D integration technology based on the wafer stacking method. We fabricated the 3D shared memory test chip with three memory layers using our 3D integration technology. It was demonstrated that the basic memory operation and the broadcast operation of 3D shared memory are successfully performed.

Original language	English
Pages (from-to)	165-167
Number of pages	3
Journal	Technical Digest - International Electron Devices Meeting
Publication status	Published - 2000
Externally published	Yes
Event	2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States Duration: 2000 Dec 10 → 2000 Dec 13

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

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title = "Three-dimensional shared memory fabricated using wafer stacking technology",

abstract = "We proposed a new three-dimensional (3D) shared memory for a high performance parallel processor system. In order to realize such new 3D shared memory, we have developed a new 3D integration technology based on the wafer stacking method. We fabricated the 3D shared memory test chip with three memory layers using our 3D integration technology. It was demonstrated that the basic memory operation and the broadcast operation of 3D shared memory are successfully performed.",

author = "Lee, {K. W.} and T. Nakamura and T. Ono and Y. Yamada and T. Mizukusa and H. Hashimoto and Park, {K. T.} and H. Kurino and M. Koyanagi",

year = "2000",

language = "English",

pages = "165--167",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2000 IEEE International Electron Devices Meeting ; Conference date: 10-12-2000 Through 13-12-2000",

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TY - JOUR

T1 - Three-dimensional shared memory fabricated using wafer stacking technology

AU - Lee, K. W.

AU - Nakamura, T.

AU - Ono, T.

AU - Yamada, Y.

AU - Mizukusa, T.

AU - Hashimoto, H.

AU - Park, K. T.

AU - Kurino, H.

AU - Koyanagi, M.

PY - 2000

Y1 - 2000

N2 - We proposed a new three-dimensional (3D) shared memory for a high performance parallel processor system. In order to realize such new 3D shared memory, we have developed a new 3D integration technology based on the wafer stacking method. We fabricated the 3D shared memory test chip with three memory layers using our 3D integration technology. It was demonstrated that the basic memory operation and the broadcast operation of 3D shared memory are successfully performed.

AB - We proposed a new three-dimensional (3D) shared memory for a high performance parallel processor system. In order to realize such new 3D shared memory, we have developed a new 3D integration technology based on the wafer stacking method. We fabricated the 3D shared memory test chip with three memory layers using our 3D integration technology. It was demonstrated that the basic memory operation and the broadcast operation of 3D shared memory are successfully performed.

UR - http://www.scopus.com/inward/record.url?scp=0034453365&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034453365&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0034453365

SP - 165

EP - 167

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

SN - 0163-1918

T2 - 2000 IEEE International Electron Devices Meeting

Y2 - 10 December 2000 through 13 December 2000

ER -

Three-dimensional shared memory fabricated using wafer stacking technology

Abstract

ASJC Scopus subject areas

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