TY - GEN
T1 - Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bonding
AU - Koyanagi, Mitsumasa
AU - Fukushima, Takafumi
AU - Tanaka, Tetsu
PY - 2010/12/13
Y1 - 2010/12/13
N2 - Three-dimensional (3-D) integration technologies using through-silicon vias (TSV's) are described. We have developed a 3-D integration technology using TSV's based on a wafer-to-wafer bonding method for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have developed a new 3-D integration technology based on a reconfigured wafer-to-wafer bonding method called a super-chip integration. A number of known good dies (KGDs) are simultaneously aligned and bonded onto lower chips or wafers with high alignment accuracy by using a new self-assembly technique in a super-chip integration.
AB - Three-dimensional (3-D) integration technologies using through-silicon vias (TSV's) are described. We have developed a 3-D integration technology using TSV's based on a wafer-to-wafer bonding method for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have developed a new 3-D integration technology based on a reconfigured wafer-to-wafer bonding method called a super-chip integration. A number of known good dies (KGDs) are simultaneously aligned and bonded onto lower chips or wafers with high alignment accuracy by using a new self-assembly technique in a super-chip integration.
UR - http://www.scopus.com/inward/record.url?scp=78649810896&partnerID=8YFLogxK
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U2 - 10.1109/CICC.2010.5617626
DO - 10.1109/CICC.2010.5617626
M3 - Conference contribution
AN - SCOPUS:78649810896
SN - 9781424457588
T3 - Proceedings of the Custom Integrated Circuits Conference
BT - IEEE Custom Integrated Circuits Conference 2010, CICC 2010
T2 - 32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010
Y2 - 19 September 2010 through 22 September 2010
ER -