Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bonding

Mitsumasa Koyanagi; Takafumi Fukushima; Tetsu Tanaka

doi:10.1109/CICC.2010.5617626

Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bonding

Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

Three-dimensional (3-D) integration technologies using through-silicon vias (TSV's) are described. We have developed a 3-D integration technology using TSV's based on a wafer-to-wafer bonding method for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have developed a new 3-D integration technology based on a reconfigured wafer-to-wafer bonding method called a super-chip integration. A number of known good dies (KGDs) are simultaneously aligned and bonded onto lower chips or wafers with high alignment accuracy by using a new self-assembly technique in a super-chip integration.

Original language	English
Title of host publication	IEEE Custom Integrated Circuits Conference 2010, CICC 2010
DOIs	https://doi.org/10.1109/CICC.2010.5617626
Publication status	Published - 2010 Dec 13
Event	32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010 - San Jose, CA, United States Duration: 2010 Sep 19 → 2010 Sep 22

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Other

Other	32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010
Country/Territory	United States
City	San Jose, CA
Period	10/9/19 → 10/9/22

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/CICC.2010.5617626

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Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bonding. / Koyanagi, Mitsumasa; Fukushima, Takafumi ; Tanaka, Tetsu.

IEEE Custom Integrated Circuits Conference 2010, CICC 2010. 2010. 5617626 (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Koyanagi, M, Fukushima, T & Tanaka, T 2010, Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bonding. in IEEE Custom Integrated Circuits Conference 2010, CICC 2010., 5617626, Proceedings of the Custom Integrated Circuits Conference, 32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010, San Jose, CA, United States, 10/9/19. https://doi.org/10.1109/CICC.2010.5617626

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title = "Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bonding",

abstract = "Three-dimensional (3-D) integration technologies using through-silicon vias (TSV's) are described. We have developed a 3-D integration technology using TSV's based on a wafer-to-wafer bonding method for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have developed a new 3-D integration technology based on a reconfigured wafer-to-wafer bonding method called a super-chip integration. A number of known good dies (KGDs) are simultaneously aligned and bonded onto lower chips or wafers with high alignment accuracy by using a new self-assembly technique in a super-chip integration.",

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AB - Three-dimensional (3-D) integration technologies using through-silicon vias (TSV's) are described. We have developed a 3-D integration technology using TSV's based on a wafer-to-wafer bonding method for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have developed a new 3-D integration technology based on a reconfigured wafer-to-wafer bonding method called a super-chip integration. A number of known good dies (KGDs) are simultaneously aligned and bonded onto lower chips or wafers with high alignment accuracy by using a new self-assembly technique in a super-chip integration.

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Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bonding

Abstract

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