Three-dimensional integration technology using self-assembly technique and super-chip integration

Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

We have proposed a new three-dimensional (3-D) integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration. It was confirmed that Si chips with sizes of 1 mm square to 5 mm square were precisely assembled on Si wafers with high alignment accuracy of less than 0.5μm. We have fabricated 3-D LSI test chips by a super-chip integration technology.

Original languageEnglish
Title of host publication2008 IEEE International Interconnect Technology Conference, IITC
Pages10-12
Number of pages3
DOIs
Publication statusPublished - 2008 Sep 9
Event2008 IEEE International Interconnect Technology Conference, IITC - Burlingame, CA, United States
Duration: 2008 Jun 12008 Jun 4

Publication series

Name2008 IEEE International Interconnect Technology Conference, IITC

Other

Other2008 IEEE International Interconnect Technology Conference, IITC
CountryUnited States
CityBurlingame, CA
Period08/6/108/6/4

Keywords

  • Chip-to-wafer bonding
  • Self-assembly
  • Super-chip
  • Three-dimensional (3-D) LSI
  • Through-silicon-via (TSV)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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