Three-dimensional integration technology based on wafer bonding with vertical buried interconnections

Mitsumasa Koyanagi, Tomonori Nakamura, Yuusuke Yamada, Hirokazu Kikuchi, Takafumi Fukushima, Tetsu Tanaka, Hiroyuki Kurino

Research output: Contribution to journalArticlepeer-review

209 Citations (Scopus)

Abstract

A three-dimensional (3-D) integration technology has been developed for the fabrication of a new 3-D shared-memory test chip. This 3-D technology is based on the wafer bonding and thinning method. Five key technologies for 3-D integration were developed, namely, the formation of vertical buried interconnections, metal microbump formations, stacked wafer thinning, wafer alignment, and wafer bonding. Deep trenches having a diameter of 2 μm and a depth of approximately 50 μm were formed in the silicon substrate using inductively coupled plasma etching to form vertical buried interconnections. These trenches were oxidized and filled with n+ polycrystalline silicon or tungsten. The 3-D devices and 3-D shared-memory test chips with three-stacked layers were fabricated by bonding the wafers with vertical buried interconnections after thinning. No characteristic degradation was observed in the fabricated 3-D devices. It was confirmed that fundamental memory operation and broadcast operation between the three memory layers could be successfully performed in the fabricated 3-D shared-memory test chip.

Original languageEnglish
Pages (from-to)2799-2808
Number of pages10
JournalIEEE Transactions on Electron Devices
Volume53
Issue number11
DOIs
Publication statusPublished - 2006 Nov 1

Keywords

  • 3-D memory
  • Buried interconnection
  • Microbump
  • Three-dimensional (3-D) large-scare integration (LSI)
  • Wafer bonding

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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