Three-dimensional integration technology and integrated systems

Mitsumasa Koyanagi; Takafumi Fukushima; Tetsu Tanaka

doi:10.1109/ASPDAC.2009.4796515

Three-dimensional integration technology and integrated systems

Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

32 Citations (Scopus)

Abstract

A three-dimensional (3-D) integration technology based on the wafer-to-wafer bonding using through silicon vias (TSV's) has been developed for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have proposed a new reconfigurable parallel image processing system. To achieve this system, we have proposed a new 3-D integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration.

Original language	English
Title of host publication	Proceedings of the ASP-DAC 2009
Subtitle of host publication	Asia and South Pacific Design Automation Conference 2009
Pages	409-415
Number of pages	7
DOIs	https://doi.org/10.1109/ASPDAC.2009.4796515
Publication status	Published - 2009 Apr 20
Event	Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 - Yokohama, Japan Duration: 2009 Jan 19 → 2009 Jan 22

Other

Other	Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
Country	Japan
City	Yokohama
Period	09/1/19 → 09/1/22

ASJC Scopus subject areas

Electrical and Electronic Engineering
Computer Science Applications
Computer Graphics and Computer-Aided Design

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abstract = "A three-dimensional (3-D) integration technology based on the wafer-to-wafer bonding using through silicon vias (TSV's) has been developed for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have proposed a new reconfigurable parallel image processing system. To achieve this system, we have proposed a new 3-D integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration.",

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