Three-dimensional integration technology and integrated systems

Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

32 Citations (Scopus)

Abstract

A three-dimensional (3-D) integration technology based on the wafer-to-wafer bonding using through silicon vias (TSV's) has been developed for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have proposed a new reconfigurable parallel image processing system. To achieve this system, we have proposed a new 3-D integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2009
Subtitle of host publicationAsia and South Pacific Design Automation Conference 2009
Pages409-415
Number of pages7
DOIs
Publication statusPublished - 2009 Apr 20
EventAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 - Yokohama, Japan
Duration: 2009 Jan 192009 Jan 22

Other

OtherAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
CountryJapan
CityYokohama
Period09/1/1909/1/22

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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    Koyanagi, M., Fukushima, T., & Tanaka, T. (2009). Three-dimensional integration technology and integrated systems. In Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009 (pp. 409-415). [4796515] https://doi.org/10.1109/ASPDAC.2009.4796515