Thermal Stress in Silicon Chips Encapsulated in IC PLastic Packages under Temperature Cycling

Hideo Miura, Makoto Kitano, Asao Nishimura, Sueo Kawai, Kunihiko Nishi

Research output: Contribution to journalArticlepeer-review

Abstract

The thermal stress in silicon chips encapsulated in IC plastic packages under temperature cycling was discussed. Stress-sensing chips utilizing the piezoresistive effect were used for the stress measurement. It was found that the chip stress increased gradually with increase of the number of temperature cycles between -55 °C and 150 °C. The reason for this increase of the chip stress was explained by considering viscoelastic phenomena of the resin material used for the encapsulation of packages. When the holding time at 150 °C was shorter than the stress relaxation time of the resin at that temperature, this stress increase was observed. It was found analytically that this stress increase could be more than 10% when the holding time was much shorter than the stress relaxation time of the resin.

Original languageEnglish
Pages (from-to)2415-2421
Number of pages7
JournalTransactions of the Japan Society of Mechanical Engineers Series A
Volume57
Issue number542
DOIs
Publication statusPublished - 1991
Externally publishedYes

Keywords

  • Experimental Stress Analysis
  • High Polymer Materials
  • Numerical Analysis
  • Structural Reliability
  • Thermal Stress
  • Viscoelasticity

ASJC Scopus subject areas

  • Materials Science(all)
  • Mechanics of Materials
  • Mechanical Engineering

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