The potential of on-chip memory systems for future vector architectures

Hiroaki Kobayashi, Akihiko Musa, Yoshiei Sato, Hiroyuki Takizawa, Koki Okabe

Research output: Contribution to conferencePaperpeer-review

6 Citations (Scopus)


Summary In this paper, we have discussed the potential of on-chip memory subsystems for future vector architectures. The performance evaluation based on the early experiments suggests that even with moderate-sized on-chip cache with 512KB to 2MB, it covered a lack of the memory bandwidths of vector load/store units with 2B/flop or lower, and boosted the sustained system performance up to the level of the 4B/flop performance. Selective caching, in which only the data with the high locality of reference are cached, is also effective for efficient use of limited on-chip caches.

Original languageEnglish
Number of pages18
Publication statusPublished - 2008 Jan 1
Event2007 7th Teraflop Workshop - Sendai, Japan
Duration: 2007 Nov 212007 Nov 22


Other2007 7th Teraflop Workshop

ASJC Scopus subject areas

  • Software


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