The performance of magnetic tunnel junction integrated on the back-end metal line of complimentary metal-oxide-semiconductor circuits

Tetsuo Endoh, Fumitaka Iga, Shoji Ikeda, Katsuya Miura, Jun Hayakawa, Masashi Kamiyanagi, Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno

Research output: Contribution to journalArticle

Abstract

In this paper, we have described the complementary metal-oxide- semiconductor (CMOS)/magnetic tunnel junction (MTJ) integrated process technology; MTJs were fabricated on via metal with surface roughness of 0.3nm with 0.14 μ CMOS process and 60 × 180nm2 MTJ process. It is shown that by this process technology, the fabricated MTJ on CMOS logic circuit plane achieves a large change in a resistance of 3.63 kω (anti-parallel) with the TMR ratio of 138% at room temperature, which is large enough for a sensing scheme of standard CMOS logic. Furthermore, we have successfully demonstrated the DC and AC operation of this MTJ with write transistors. As the results, our MTJ achieves high enough write/read performance with transistors for realizing MTJ-based logic circuits.

Original languageEnglish
Article number04DM06
JournalJapanese journal of applied physics
Volume49
Issue number4 PART 2
DOIs
Publication statusPublished - 2010 Apr 1

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

Fingerprint Dive into the research topics of 'The performance of magnetic tunnel junction integrated on the back-end metal line of complimentary metal-oxide-semiconductor circuits'. Together they form a unique fingerprint.

  • Cite this