Abstract
A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for single chip emulation system is developed. It demonstrates the sequential execution of sub-circuits divided from original circuit, by newly developed Temporal Communication Module (TCM). In order to accelerate emulation speed, a logic element, which can reduce configuration data by 30% as compared to conventional Look-Up-Table, is implemented. The chip (3.9×3.9mm 2) fabricated with 0.6 μm CMOS technology operates at 33 MHz with 5.0 V power supply.
Original language | English |
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Pages | 279-282 |
Number of pages | 4 |
Publication status | Published - 2003 Oct 1 |
Event | 2003 Symposium on VLSI Circuits - Kyoto, Japan Duration: 2003 Jun 12 → 2003 Jun 14 |
Other
Other | 2003 Symposium on VLSI Circuits |
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Country/Territory | Japan |
City | Kyoto |
Period | 03/6/12 → 03/6/14 |
Keywords
- Emulation
- Logic element
- Reconfigurable
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering