The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration

Takeshi Ohkawa; Toshiyuki Nozawa; Masanori Fujibayashi; Naoto Miyamoto; Karnan Leo; Soichiro Kita; Koji Kotani; Tadahiro Ohmi

The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration

Takeshi Ohkawa, Toshiyuki Nozawa, Masanori Fujibayashi, Naoto Miyamoto, Karnan Leo, Soichiro Kita, Koji Kotani, Tadahiro Ohmi

Research output: Contribution to conference › Paper › peer-review

Abstract

A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for a single chip emulation system is developed. It demonstrates the sequential execution of several sub-circuits divided temporally from an original large circuit. In order to accelerate emulation speed, a logic element, reducing total configuration data by 30% compared to conventional Look-Up-Table, and Temporal Communication Module (TCM) to support save/restore of circuit state and data communication among divided sub-circuits, are implemented on the Flexible Processor.

Original language	English
Pages	557-558
Number of pages	2
Publication status	Published - 2004 Jun 1
Event	Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan Duration: 2004 Jan 27 → 2004 Jan 30

Other

Other	Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
Country	Japan
City	Yokohama
Period	04/1/27 → 04/1/30

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration'. Together they form a unique fingerprint.

Cite this

The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration. / Ohkawa, Takeshi; Nozawa, Toshiyuki; Fujibayashi, Masanori; Miyamoto, Naoto; Leo, Karnan; Kita, Soichiro; Kotani, Koji; Ohmi, Tadahiro.

2004. 557-558 Paper presented at Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, Yokohama, Japan.

Research output: Contribution to conference › Paper › peer-review

Ohkawa, Takeshi ; Nozawa, Toshiyuki ; Fujibayashi, Masanori ; Miyamoto, Naoto ; Leo, Karnan ; Kita, Soichiro ; Kotani, Koji ; Ohmi, Tadahiro. / The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration. Paper presented at Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, Yokohama, Japan.2 p.

@conference{92dfcac561434033b2ac6a86f5e9a805,

title = "The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration",

abstract = "A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for a single chip emulation system is developed. It demonstrates the sequential execution of several sub-circuits divided temporally from an original large circuit. In order to accelerate emulation speed, a logic element, reducing total configuration data by 30% compared to conventional Look-Up-Table, and Temporal Communication Module (TCM) to support save/restore of circuit state and data communication among divided sub-circuits, are implemented on the Flexible Processor.",

author = "Takeshi Ohkawa and Toshiyuki Nozawa and Masanori Fujibayashi and Naoto Miyamoto and Karnan Leo and Soichiro Kita and Koji Kotani and Tadahiro Ohmi",

year = "2004",

month = jun,

day = "1",

language = "English",

pages = "557--558",

note = "Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 ; Conference date: 27-01-2004 Through 30-01-2004",

}

TY - CONF

T1 - The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration

AU - Ohkawa, Takeshi

AU - Nozawa, Toshiyuki

AU - Fujibayashi, Masanori

AU - Miyamoto, Naoto

AU - Leo, Karnan

AU - Kita, Soichiro

AU - Kotani, Koji

AU - Ohmi, Tadahiro

PY - 2004/6/1

Y1 - 2004/6/1

N2 - A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for a single chip emulation system is developed. It demonstrates the sequential execution of several sub-circuits divided temporally from an original large circuit. In order to accelerate emulation speed, a logic element, reducing total configuration data by 30% compared to conventional Look-Up-Table, and Temporal Communication Module (TCM) to support save/restore of circuit state and data communication among divided sub-circuits, are implemented on the Flexible Processor.

AB - A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for a single chip emulation system is developed. It demonstrates the sequential execution of several sub-circuits divided temporally from an original large circuit. In order to accelerate emulation speed, a logic element, reducing total configuration data by 30% compared to conventional Look-Up-Table, and Temporal Communication Module (TCM) to support save/restore of circuit state and data communication among divided sub-circuits, are implemented on the Flexible Processor.

UR - http://www.scopus.com/inward/record.url?scp=2442597050&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=2442597050&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:2442597050

SP - 557

EP - 558

T2 - Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004

Y2 - 27 January 2004 through 30 January 2004

ER -

The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration

Abstract

Other

ASJC Scopus subject areas

Other files and links

Cite this