The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration

Takeshi Ohkawa; Toshiyuki Nozawa; Masanori Fujibayashi; Naoto Miyamoto; Karnan Leo; Soichiro Kita; Koji Kotani; Tadahiro Ohmi

The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration

Takeshi Ohkawa, Toshiyuki Nozawa, Masanori Fujibayashi, Naoto Miyamoto, Karnan Leo, Soichiro Kita, Koji Kotani, Tadahiro Ohmi

Research output: Contribution to conference › Paper › peer-review

Abstract

A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for a single chip emulation system is developed. It demonstrates the sequential execution of several sub-circuits divided temporally from an original large circuit. In order to accelerate emulation speed, a logic element, reducing total configuration data by 30% compared to conventional Look-Up-Table, and Temporal Communication Module (TCM) to support save/restore of circuit state and data communication among divided sub-circuits, are implemented on the Flexible Processor.

Original language	English
Pages	557-558
Number of pages	2
Publication status	Published - 2004 Jun 1
Event	Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan Duration: 2004 Jan 27 → 2004 Jan 30

Other

Other	Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
Country/Territory	Japan
City	Yokohama
Period	04/1/27 → 04/1/30

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Cite this

The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration. / Ohkawa, Takeshi; Nozawa, Toshiyuki; Fujibayashi, Masanori et al.

2004. 557-558 Paper presented at Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, Yokohama, Japan.

Research output: Contribution to conference › Paper › peer-review

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AU - Ohkawa, Takeshi

AU - Nozawa, Toshiyuki

AU - Fujibayashi, Masanori

AU - Miyamoto, Naoto

AU - Leo, Karnan

AU - Kita, Soichiro

AU - Kotani, Koji

AU - Ohmi, Tadahiro

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N2 - A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for a single chip emulation system is developed. It demonstrates the sequential execution of several sub-circuits divided temporally from an original large circuit. In order to accelerate emulation speed, a logic element, reducing total configuration data by 30% compared to conventional Look-Up-Table, and Temporal Communication Module (TCM) to support save/restore of circuit state and data communication among divided sub-circuits, are implemented on the Flexible Processor.

AB - A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for a single chip emulation system is developed. It demonstrates the sequential execution of several sub-circuits divided temporally from an original large circuit. In order to accelerate emulation speed, a logic element, reducing total configuration data by 30% compared to conventional Look-Up-Table, and Temporal Communication Module (TCM) to support save/restore of circuit state and data communication among divided sub-circuits, are implemented on the Flexible Processor.

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T2 - Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004

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The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration

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ASJC Scopus subject areas

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