The Charge-Pumping Technique for Grain Boundary Trap Evaluation in Poly silicon TFT’s

Mitsumasa Koyanagi, Yoshihiro Baba, Kiyomi Hata, I. Wei Wu, Alan G. Lewis, Richard Bruce, Mario Fuse

Research output: Contribution to journalArticlepeer-review

29 Citations (Scopus)


We have exploited both the attractive transport properties and the etch selectivity of InP in a novel InAlAs/n+-InP metal-insulator-doped-channel heterostructure FET (MID-FET). In several other material systems, the MIDFET has been shown to be well-suited to high-power telecommunications applications. Our device employs InP both as the channel layer as well as an etch-stop layer in a selective-etch recessed-gate process. Lg =1.8-μm devices achieve gm and ID,max values of 224 mS/mm and 408 mA/mm, respectively, the highest reported values for any InP channel HFET with Lg≥ 0.8 μm, including MODFET’s. These figures combine with a breakdown voltage of 10 V, and peak values of fT and fmax of 10.5 and 28 GHz, respectively. Our selective-etch recessed-gate process contributes to excellent device performance while maintaining a tight 60-mV threshold voltage distribution (13 mV between adjacent devices).

Original languageEnglish
Pages (from-to)152-154
Number of pages3
JournalIEEE Electron Device Letters
Issue number3
Publication statusPublished - 1992 Mar
Externally publishedYes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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