Temporal circuit partitioning for a 90nm CMOS multi-context FPGA and its delay measurement

Naoto Miyamoto, Tadahiro Ohmi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, we present a dynamically reconfigurable multi-context FPGA named Flexible Processor (FP) equipped with shift-register temporal communication module (SR-TCM). Temporal partitioning algorithm has been developed, which divides a long critical path into equal-length short paths context-wise. From measurement results of a FP fabricated by using a 90nm CMOS technology, it is found that the execution latency remains constant regardless of the number of contexts used.

Original languageEnglish
Title of host publication2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Pages373-374
Number of pages2
DOIs
Publication statusPublished - 2010
Event2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei, Taiwan, Province of China
Duration: 2010 Jan 182010 Jan 21

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
CountryTaiwan, Province of China
CityTaipei
Period10/1/1810/1/21

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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