Technology and device design constraints for low voltage-low power sub-0.1 μm CMOS devices

Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The device structure and the device design methodology to achieve the low voltage-low power sub-0.1 μm MOS devices are discussed. It is shown in the simulation that it is difficult to simultaneously satisfy two requirements to suppress the short channel effect and to improve the device performance in the sub-0.1 μm devices. It is experimentally demonstrated that the short channel effect can be sufficiently suppressed by employing the double punchthrough stopper structure even in the sub-0.1 μ m devices with the gate length of 0.07 μ m if the reduced improvement of the device performance is allowed.

Original languageEnglish
Title of host publicationESSDERC 1993 - Proceedings of the 23rd European Solid State Device Research Conference
EditorsJ. P. Noblanc, P. Gentil, M. Verdone, J. Borel, A. Nouailhat
PublisherIEEE Computer Society
Pages935-942
Number of pages8
ISBN (Electronic)2863321358
ISBN (Print)9782863321355
Publication statusPublished - 1993 Jan 1
Event23rd European Solid State Device Research Conference, ESSDERC 1993 - Grenoble, France
Duration: 1993 Sep 131993 Sep 16

Publication series

NameEuropean Solid-State Device Research Conference
ISSN (Print)1930-8876

Other

Other23rd European Solid State Device Research Conference, ESSDERC 1993
CountryFrance
CityGrenoble
Period93/9/1393/9/16

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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  • Cite this

    Koyanagi, M. (1993). Technology and device design constraints for low voltage-low power sub-0.1 μm CMOS devices. In J. P. Noblanc, P. Gentil, M. Verdone, J. Borel, & A. Nouailhat (Eds.), ESSDERC 1993 - Proceedings of the 23rd European Solid State Device Research Conference (pp. 935-942). [5435638] (European Solid-State Device Research Conference). IEEE Computer Society.