Ta/Mo stack dual metal gate technology applicable to gate-first processes

Takashi Matsukawa; Yongxun Liu; Kazuhiko Endo; Meishoku Masahara; Kenichi Ishii; Hiromi Yamauchi; Junichi Tsukada; Eiichi Suzuki

doi:10.1143/JJAP.46.1825

Ta/Mo stack dual metal gate technology applicable to gate-first processes

Takashi Matsukawa, Yongxun Liu, Kazuhiko Endo, Meishoku Masahara, Kenichi Ishii, Hiromi Yamauchi, Junichi Tsukada, Eiichi Suzuki

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

Dual metal gate technology using a combination of Mo and a Ta/Mo stack suitable for fully depleted silicon-on-insulator (FD-SOI) and double-gate (DG) transistors applicable to a gate-first process has been investigated. The annealing of the Ta/Mo stack at 600-700°C induces the diffusion of Ta into the Mo layer, and different work functions between the single Mo layer and Ta/Mo stack gates are successfully obtained. The sputtered Mo gate exhibits a higher thermal stability than the e-beam-evaporated Mo gate. The difference in flatband voltage (0.31 V) between the Mo and Ta/Mo gates is ensured even after annealing at 850°C for 20 s, by which subsequent source/drain activation can be carried out.

Original language	English
Pages (from-to)	1825-1829
Number of pages	5
Journal	Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume	46
Issue number	4 B
DOIs	https://doi.org/10.1143/JJAP.46.1825
Publication status	Published - 2007 Apr 24
Externally published	Yes

Keywords

DG-MOSFET
Dual metal
FD-SOI
Interdiffusion
Metal gate
Mo
Ta
Work function

ASJC Scopus subject areas

Engineering(all)
Physics and Astronomy(all)

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10.1143/JJAP.46.1825

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@article{2347fe3d07364ba396ce118309013c56,

title = "Ta/Mo stack dual metal gate technology applicable to gate-first processes",

abstract = "Dual metal gate technology using a combination of Mo and a Ta/Mo stack suitable for fully depleted silicon-on-insulator (FD-SOI) and double-gate (DG) transistors applicable to a gate-first process has been investigated. The annealing of the Ta/Mo stack at 600-700°C induces the diffusion of Ta into the Mo layer, and different work functions between the single Mo layer and Ta/Mo stack gates are successfully obtained. The sputtered Mo gate exhibits a higher thermal stability than the e-beam-evaporated Mo gate. The difference in flatband voltage (0.31 V) between the Mo and Ta/Mo gates is ensured even after annealing at 850°C for 20 s, by which subsequent source/drain activation can be carried out.",

keywords = "DG-MOSFET, Dual metal, FD-SOI, Interdiffusion, Metal gate, Mo, Ta, Work function",

author = "Takashi Matsukawa and Yongxun Liu and Kazuhiko Endo and Meishoku Masahara and Kenichi Ishii and Hiromi Yamauchi and Junichi Tsukada and Eiichi Suzuki",

year = "2007",

month = apr,

day = "24",

doi = "10.1143/JJAP.46.1825",

language = "English",

volume = "46",

pages = "1825--1829",

journal = "Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes",

issn = "0021-4922",

publisher = "Japan Society of Applied Physics",

number = "4 B",

}

TY - JOUR

T1 - Ta/Mo stack dual metal gate technology applicable to gate-first processes

AU - Matsukawa, Takashi

AU - Liu, Yongxun

AU - Endo, Kazuhiko

AU - Masahara, Meishoku

AU - Ishii, Kenichi

AU - Yamauchi, Hiromi

AU - Tsukada, Junichi

AU - Suzuki, Eiichi

PY - 2007/4/24

Y1 - 2007/4/24

N2 - Dual metal gate technology using a combination of Mo and a Ta/Mo stack suitable for fully depleted silicon-on-insulator (FD-SOI) and double-gate (DG) transistors applicable to a gate-first process has been investigated. The annealing of the Ta/Mo stack at 600-700°C induces the diffusion of Ta into the Mo layer, and different work functions between the single Mo layer and Ta/Mo stack gates are successfully obtained. The sputtered Mo gate exhibits a higher thermal stability than the e-beam-evaporated Mo gate. The difference in flatband voltage (0.31 V) between the Mo and Ta/Mo gates is ensured even after annealing at 850°C for 20 s, by which subsequent source/drain activation can be carried out.

AB - Dual metal gate technology using a combination of Mo and a Ta/Mo stack suitable for fully depleted silicon-on-insulator (FD-SOI) and double-gate (DG) transistors applicable to a gate-first process has been investigated. The annealing of the Ta/Mo stack at 600-700°C induces the diffusion of Ta into the Mo layer, and different work functions between the single Mo layer and Ta/Mo stack gates are successfully obtained. The sputtered Mo gate exhibits a higher thermal stability than the e-beam-evaporated Mo gate. The difference in flatband voltage (0.31 V) between the Mo and Ta/Mo gates is ensured even after annealing at 850°C for 20 s, by which subsequent source/drain activation can be carried out.

KW - DG-MOSFET

KW - Dual metal

KW - FD-SOI

KW - Interdiffusion

KW - Metal gate

KW - Mo

KW - Ta

KW - Work function

UR - http://www.scopus.com/inward/record.url?scp=34547917295&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34547917295&partnerID=8YFLogxK

U2 - 10.1143/JJAP.46.1825

DO - 10.1143/JJAP.46.1825

M3 - Article

AN - SCOPUS:34547917295

SN - 0021-4922

VL - 46

SP - 1825

EP - 1829

JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

IS - 4 B

ER -

Ta/Mo stack dual metal gate technology applicable to gate-first processes

Abstract

Keywords

ASJC Scopus subject areas

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