Systolic computational-memory architecture for an FPGA-based flow solver

Kentaro Sano, Takanori Iizuka, Satoru Yamamoto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents an FPGA-based flow solver based on the systolic computational-memory architecture. We show that the flow solver based on the fractional-step method with difference schemes can be expressed as a systolic algorithm, and the systolic computationalmemory architecture is suitable to design the special-purpose processor for the flow solver. Based on this architecture, we propose a specialpurpose processor comprised of a 2D array of cells connected by a 2D mesh network. Each cell has a computational data-path and a local memory, While the whole array stores data as a memory, it also performs highly parallel and scalable floating-point computations with the sufficient memory bandwidth. We report the initial design of the processor for two ALTERA Stratix II FPGAs, and discuss its estimated peak performance that could reach 30 GFLOPS at only 60MHz.

Original languageEnglish
Title of host publicationProceedings of the 2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06
Pages423-427
Number of pages5
DOIs
Publication statusPublished - 2006 Dec 1
Event2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06 - San Juan, Puerto Rico
Duration: 2006 Aug 62007 Aug 9

Publication series

NameMidwest Symposium on Circuits and Systems
Volume1
ISSN (Print)1548-3746

Other

Other2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06
CountryPuerto Rico
CitySan Juan
Period06/8/607/8/9

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • Cite this

    Sano, K., Iizuka, T., & Yamamoto, S. (2006). Systolic computational-memory architecture for an FPGA-based flow solver. In Proceedings of the 2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06 (pp. 423-427). [4267166] (Midwest Symposium on Circuits and Systems; Vol. 1). https://doi.org/10.1109/MWSCAS.2006.382089