TY - GEN
T1 - Systolic computational-memory architecture for an FPGA-based flow solver
AU - Sano, Kentaro
AU - Iizuka, Takanori
AU - Yamamoto, Satoru
PY - 2006
Y1 - 2006
N2 - This paper presents an FPGA-based flow solver based on the systolic computational-memory architecture. We show that the flow solver based on the fractional-step method with difference schemes can be expressed as a systolic algorithm, and the systolic computationalmemory architecture is suitable to design the special-purpose processor for the flow solver. Based on this architecture, we propose a specialpurpose processor comprised of a 2D array of cells connected by a 2D mesh network. Each cell has a computational data-path and a local memory, While the whole array stores data as a memory, it also performs highly parallel and scalable floating-point computations with the sufficient memory bandwidth. We report the initial design of the processor for two ALTERA Stratix II FPGAs, and discuss its estimated peak performance that could reach 30 GFLOPS at only 60MHz.
AB - This paper presents an FPGA-based flow solver based on the systolic computational-memory architecture. We show that the flow solver based on the fractional-step method with difference schemes can be expressed as a systolic algorithm, and the systolic computationalmemory architecture is suitable to design the special-purpose processor for the flow solver. Based on this architecture, we propose a specialpurpose processor comprised of a 2D array of cells connected by a 2D mesh network. Each cell has a computational data-path and a local memory, While the whole array stores data as a memory, it also performs highly parallel and scalable floating-point computations with the sufficient memory bandwidth. We report the initial design of the processor for two ALTERA Stratix II FPGAs, and discuss its estimated peak performance that could reach 30 GFLOPS at only 60MHz.
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U2 - 10.1109/MWSCAS.2006.382089
DO - 10.1109/MWSCAS.2006.382089
M3 - Conference contribution
AN - SCOPUS:34748829653
SN - 1424401739
SN - 9781424401734
T3 - Midwest Symposium on Circuits and Systems
SP - 423
EP - 427
BT - Proceedings of the 2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06
T2 - 2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06
Y2 - 6 August 2006 through 9 August 2007
ER -