Systolic computational memory approach to high-speed codebook design

Kentaro Sano, Chiaki Takagi, Tadao Nakamura

Research output: Contribution to conferencePaperpeer-review

3 Citations (Scopus)

Abstract

This paper presents a systolic computational memory approach to high-speed codebook design required for vector quantization (VQ). Our proposed systolic computational memory has the advantages of both the systolic array and computational RAM: massively parallel processing capability and wide bandwidth of internal memory. By introducing deferred update of a codebook, the parallelism of the mini-max partial distortion competitive learning (MMPDCL) algorithm is enhanced and fully exploited by the proposed systolic computational memory for high-speed codebook design. The experiments of VQ-based image compression show that the FPGA-based prototype running at 33MHz achieves about 400 times faster codebook design than a software approach on a general-purpose microprocessor running at 2GHz.

Original languageEnglish
Pages334-339
Number of pages6
DOIs
Publication statusPublished - 2005 Dec 1
Event5th IEEE International Symposium on Signal Processing and Information Technology - Athens, Greece
Duration: 2005 Dec 182005 Dec 21

Other

Other5th IEEE International Symposium on Signal Processing and Information Technology
Country/TerritoryGreece
CityAthens
Period05/12/1805/12/21

Keywords

  • Codebook design
  • Computational memory
  • MMPDCL algorithm
  • Systolic architecture
  • Vector quantization

ASJC Scopus subject areas

  • Engineering(all)

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