Systematic design of High-Radix montgomery multipliers for RSA processors

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

The present paper proposes a systematic design approach to provide the optimal high-radix Montgomery multipliers for an RSA processor satisfying user requirements. We introduces three multiplier-based architectures using different intermediate-data forms ((i) single form, (ii) semi carry-save form, and (iii) carry-save form), and combined them with a wide variety of arithmetic components. Their radices are also parameterized from 28 to 2 64. A total of 202 designs for 1,024- bit RSA processors were obtained for each radix, and were synthesized using a 90-nm CMOS standard cell library. The smallest design of 0.9 Kgates with 137.8 ms/RSA to the fastest design of 1.8 ms/RSA at 74.7 Kgates were then obtained. In addition, the optimal design to meet the user requirements can be easily obtained from all the combinations. In addition to choosing the datapath architecture, the arithmetic component, and the radix parameters, the proposed systematic approach can also adopt other process technologies.

Original languageEnglish
Title of host publication26th IEEE International Conference on Computer Design 2008, ICCD
Pages416-421
Number of pages6
DOIs
Publication statusPublished - 2008 Dec 1
Event26th IEEE International Conference on Computer Design 2008, ICCD - Lake Tahoe, CA, United States
Duration: 2008 Oct 122008 Oct 15

Publication series

Name26th IEEE International Conference on Computer Design 2008, ICCD

Other

Other26th IEEE International Conference on Computer Design 2008, ICCD
CountryUnited States
CityLake Tahoe, CA
Period08/10/1208/10/15

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Miyamoto, A., Homma, N., Aoki, T., & Satoh, A. (2008). Systematic design of High-Radix montgomery multipliers for RSA processors. In 26th IEEE International Conference on Computer Design 2008, ICCD (pp. 416-421). [4751894] (26th IEEE International Conference on Computer Design 2008, ICCD). https://doi.org/10.1109/ICCD.2008.4751894