TY - GEN
T1 - System Implementation of Synchronized SS-CDMA for QZSS Safely Confirmation System
AU - Oguma, H.
AU - Kawai, R.
AU - Asai, T.
AU - Kameda, Suguru
AU - Motoyoshi, Mizuki
AU - Suematsu, N.
N1 - Funding Information:
ACKNOW LEDGMENT A part of this work is supported by JSPS KAKENHI Grant Number JP16H04361 and JP16KK0139.
Publisher Copyright:
© 2020 IEEE.
PY - 2020/10/21
Y1 - 2020/10/21
N2 - In this paper, we construct and evaluate central processing unit - intellectual property (CPU-IP) core as one of the considerations of system on chip (SoC) implementation of the transmission timing control system, in synchronized Spread-Spectrum Code-Division Multiple-Access (SS-CDMA) communication for the location and short message communication system using Quasi-Zenith Satellite System (QZSS). As a result of evaluating the transmission timing calculation unit with the CPU - IP core constructed on the field programmable gate array (FPGA), it is possible to construct a system with the same performance as that constructed with the conventional micro controller unit (MCU). In addition, we experiment with the transmission timing control by connecting the construct transmission timing calculation unit and the conventional delay control unit. As a result, the system is found to be operating normally. Since the delay control unit is a conventional one, but, this result is sufficient to result as a foothold for SoC implement of the transmission timing control system.
AB - In this paper, we construct and evaluate central processing unit - intellectual property (CPU-IP) core as one of the considerations of system on chip (SoC) implementation of the transmission timing control system, in synchronized Spread-Spectrum Code-Division Multiple-Access (SS-CDMA) communication for the location and short message communication system using Quasi-Zenith Satellite System (QZSS). As a result of evaluating the transmission timing calculation unit with the CPU - IP core constructed on the field programmable gate array (FPGA), it is possible to construct a system with the same performance as that constructed with the conventional micro controller unit (MCU). In addition, we experiment with the transmission timing control by connecting the construct transmission timing calculation unit and the conventional delay control unit. As a result, the system is found to be operating normally. Since the delay control unit is a conventional one, but, this result is sufficient to result as a foothold for SoC implement of the transmission timing control system.
KW - Central Processing Unit (CPU)
KW - Code-Division Multiple-Access (CDMA)
KW - Field Programmable Gate Array (FPGA)
KW - Global Positioning System (GPS)
KW - Quasi-Zenith Satellite System (QZSS)
KW - Satellite Communication
KW - Spread Spectrum (SS)
KW - System on Chip (SoC)
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U2 - 10.1109/ICTC49870.2020.9289560
DO - 10.1109/ICTC49870.2020.9289560
M3 - Conference contribution
AN - SCOPUS:85099003948
T3 - International Conference on ICT Convergence
SP - 105
EP - 109
BT - ICTC 2020 - 11th International Conference on ICT Convergence
PB - IEEE Computer Society
T2 - 11th International Conference on Information and Communication Technology Convergence, ICTC 2020
Y2 - 21 October 2020 through 23 October 2020
ER -