Synthesis of multiple-valued arithmetic circuits using evolutionary graph generation

Research output: Contribution to journalConference articlepeer-review

3 Citations (Scopus)

Abstract

This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the transistor-level design of multiple-valued arithmetic circuits. An important feature of EGG is its capability to optimize general graph structures directly instead of encoding the structures into indirect representations, such as bit strings and trees. The potential capability of EGG is demonstrated through an experimental synthesis of a radix-4 signed-digit full adder circuit.

Original languageEnglish
Pages (from-to)253-258
Number of pages6
JournalProceedings of The International Symposium on Multiple-Valued Logic
Publication statusPublished - 2001 Jan 1
Event31st IEEE International Symposium on Multiple-Valued Logic (ISMVL 2001) - Warsaw, Poland
Duration: 2001 May 222001 May 24

ASJC Scopus subject areas

  • Chemical Health and Safety
  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality
  • Logic

Fingerprint Dive into the research topics of 'Synthesis of multiple-valued arithmetic circuits using evolutionary graph generation'. Together they form a unique fingerprint.

Cite this