Abstract
Synchronising logic gates (SLGs) used for a wave-pipelining design are presented. An SLG is a dual-rail logic gate which has an almost constant gate delay and can be used as an intermediate latch to synchronise data paths. Based on the SLGs, the wave-pipelining circuits are easily designed without complicated timing analysis. To evaluate the SLGs, an 8 × 8 multiplier is designed using a 90 nm design rule. The multiplier works well at 3.57 GHz.
Original language | English |
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Pages (from-to) | 1116-1117 |
Number of pages | 2 |
Journal | Electronics Letters |
Volume | 46 |
Issue number | 16 |
DOIs | |
Publication status | Published - 2010 Aug 5 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering