Synchronising logic gates for wave-pipelining design

Z. Xia; S. Ishihara; Masanori Hariyama; Michitaka Kameyama

doi:10.1049/el.2010.1602

Synchronising logic gates for wave-pipelining design

Z. Xia, S. Ishihara, Masanori Hariyama, Michitaka Kameyama

INF - Computer and Mathematical Sciences

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

Synchronising logic gates (SLGs) used for a wave-pipelining design are presented. An SLG is a dual-rail logic gate which has an almost constant gate delay and can be used as an intermediate latch to synchronise data paths. Based on the SLGs, the wave-pipelining circuits are easily designed without complicated timing analysis. To evaluate the SLGs, an 8 × 8 multiplier is designed using a 90 nm design rule. The multiplier works well at 3.57 GHz.

Original language	English
Pages (from-to)	1116-1117
Number of pages	2
Journal	Electronics Letters
Volume	46
Issue number	16
DOIs	https://doi.org/10.1049/el.2010.1602
Publication status	Published - 2010 Aug 5

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el.2010.1602

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AU - Xia, Z.

AU - Ishihara, S.

AU - Hariyama, Masanori

AU - Kameyama, Michitaka

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Y1 - 2010/8/5

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AB - Synchronising logic gates (SLGs) used for a wave-pipelining design are presented. An SLG is a dual-rail logic gate which has an almost constant gate delay and can be used as an intermediate latch to synchronise data paths. Based on the SLGs, the wave-pipelining circuits are easily designed without complicated timing analysis. To evaluate the SLGs, an 8 × 8 multiplier is designed using a 90 nm design rule. The multiplier works well at 3.57 GHz.

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Synchronising logic gates for wave-pipelining design

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