Switch block architecture for multi-context FPGAs using hybrid multiple-valued/binary context switching signals

Yoshihiro Nakatani; Masanori Hariyama; Michitaka Kameyama

doi:10.1109/ISMVL.2006.40

Switch block architecture for multi-context FPGAs using hybrid multiple-valued/binary context switching signals

Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Multi-context (MC) FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant overhead in area and power consumption. This paper presents two key technologies. The first is a floating-gate-MOS functional pass gate that merges storage and switching functions area-efficiently. The second is the use of a hybrid multiple-valued/binary context switching signal that eliminates redundancy of a conventional MC-switch with high scalability. The transistor count of the proposed MC-switch is reduced to 7% in comparison with that of a SRAM-based one.

Original language	English
Title of host publication	36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
Number of pages	1
DOIs	https://doi.org/10.1109/ISMVL.2006.40
Publication status	Published - 2006 Nov 21
Event	36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006 - Singapore, Singapore Duration: 2006 May 17 → 2006 May 20

Publication series

Name	Proceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)	0195-623X

Other

Other	36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
Country/Territory	Singapore
City	Singapore
Period	06/5/17 → 06/5/20

ASJC Scopus subject areas

Computer Science(all)
Mathematics(all)

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10.1109/ISMVL.2006.40

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Switch block architecture for multi-context FPGAs using hybrid multiple-valued/binary context switching signals. / Nakatani, Yoshihiro; Hariyama, Masanori; Kameyama, Michitaka.

36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006. 2006. 1623969 (Proceedings of The International Symposium on Multiple-Valued Logic).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nakatani, Y, Hariyama, M & Kameyama, M 2006, Switch block architecture for multi-context FPGAs using hybrid multiple-valued/binary context switching signals. in 36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006., 1623969, Proceedings of The International Symposium on Multiple-Valued Logic, 36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006, Singapore, Singapore, 06/5/17. https://doi.org/10.1109/ISMVL.2006.40

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abstract = "Multi-context (MC) FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant overhead in area and power consumption. This paper presents two key technologies. The first is a floating-gate-MOS functional pass gate that merges storage and switching functions area-efficiently. The second is the use of a hybrid multiple-valued/binary context switching signal that eliminates redundancy of a conventional MC-switch with high scalability. The transistor count of the proposed MC-switch is reduced to 7% in comparison with that of a SRAM-based one.",

author = "Yoshihiro Nakatani and Masanori Hariyama and Michitaka Kameyama",

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N2 - Multi-context (MC) FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant overhead in area and power consumption. This paper presents two key technologies. The first is a floating-gate-MOS functional pass gate that merges storage and switching functions area-efficiently. The second is the use of a hybrid multiple-valued/binary context switching signal that eliminates redundancy of a conventional MC-switch with high scalability. The transistor count of the proposed MC-switch is reduced to 7% in comparison with that of a SRAM-based one.

AB - Multi-context (MC) FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant overhead in area and power consumption. This paper presents two key technologies. The first is a floating-gate-MOS functional pass gate that merges storage and switching functions area-efficiently. The second is the use of a hybrid multiple-valued/binary context switching signal that eliminates redundancy of a conventional MC-switch with high scalability. The transistor count of the proposed MC-switch is reduced to 7% in comparison with that of a SRAM-based one.

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Switch block architecture for multi-context FPGAs using hybrid multiple-valued/binary context switching signals

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