Switch block architecture for multi-context FPGAs using hybrid multiple-valued/binary context switching signals

Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Multi-context (MC) FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant overhead in area and power consumption. This paper presents two key technologies. The first is a floating-gate-MOS functional pass gate that merges storage and switching functions area-efficiently. The second is the use of a hybrid multiple-valued/binary context switching signal that eliminates redundancy of a conventional MC-switch with high scalability. The transistor count of the proposed MC-switch is reduced to 7% in comparison with that of a SRAM-based one.

Original languageEnglish
Title of host publication36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
Number of pages1
DOIs
Publication statusPublished - 2006 Nov 21
Event36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006 - Singapore, Singapore
Duration: 2006 May 172006 May 20

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
CountrySingapore
CitySingapore
Period06/5/1706/5/20

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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