TY - GEN
T1 - Switch block architecture for multi-context FPGAs using hybrid multiple-valued/binary context switching signals
AU - Nakatani, Yoshihiro
AU - Hariyama, Masanori
AU - Kameyama, Michitaka
PY - 2006/11/21
Y1 - 2006/11/21
N2 - Multi-context (MC) FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant overhead in area and power consumption. This paper presents two key technologies. The first is a floating-gate-MOS functional pass gate that merges storage and switching functions area-efficiently. The second is the use of a hybrid multiple-valued/binary context switching signal that eliminates redundancy of a conventional MC-switch with high scalability. The transistor count of the proposed MC-switch is reduced to 7% in comparison with that of a SRAM-based one.
AB - Multi-context (MC) FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant overhead in area and power consumption. This paper presents two key technologies. The first is a floating-gate-MOS functional pass gate that merges storage and switching functions area-efficiently. The second is the use of a hybrid multiple-valued/binary context switching signal that eliminates redundancy of a conventional MC-switch with high scalability. The transistor count of the proposed MC-switch is reduced to 7% in comparison with that of a SRAM-based one.
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U2 - 10.1109/ISMVL.2006.40
DO - 10.1109/ISMVL.2006.40
M3 - Conference contribution
AN - SCOPUS:33751051158
SN - 0769525326
SN - 9780769525327
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
BT - 36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
T2 - 36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
Y2 - 17 May 2006 through 20 May 2006
ER -