SW and HW co-design of Connect6 accelerator with scalable streaming cores

Kentaro Sano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents software and hardware co-design of an FPGA-based Connect6 solver with scalable streaming cores. The solver searches a game tree by using the miniMax algorithm with alpha-beta pruning. Since evaluation of board situations is the most time-consuming part, we adopted an approach to accelerate it with dedicated hardware while other parts are executed by software. We design a custom accelerator composed of multiple streaming-cores, each of which independently evaluates possible connectabilities with six stones. We use the ALTERA's SOPC (system on programmable chip) development tool to implement the system, which contains an NIOS II processor and the custom accelerator. The implemented system operates at 100 MHz on ALTERA Cyclone IV EP4CE115 FPGA of DE2-115 board. We could implement up to 32 streaming-cores on the FPGA. In a preliminary experiment where only a single core is used to search a game tree with a depth of 1, the FPGA-based solver wins against the given software opponent at a rate of 100 % with 33.2 stones on average.

Original languageEnglish
Title of host publication2011 International Conference on Field-Programmable Technology, FPT 2011
DOIs
Publication statusPublished - 2011 Dec 1
Event2011 International Conference on Field-Programmable Technology, FPT 2011 - New Delhi, India
Duration: 2011 Dec 122011 Dec 14

Publication series

Name2011 International Conference on Field-Programmable Technology, FPT 2011

Other

Other2011 International Conference on Field-Programmable Technology, FPT 2011
CountryIndia
CityNew Delhi
Period11/12/1211/12/14

ASJC Scopus subject areas

  • Computational Mathematics

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